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p–n junction

About: p–n junction is a research topic. Over the lifetime, 7701 publications have been published within this topic receiving 108890 citations. The topic is also known as: p-n junction.


Papers
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Journal ArticleDOI
TL;DR: In this article, a new type of light-emitting diode based on a porous silicon and microcrystalline silicon carbide pn junction was fabricated, and the visible light emission from 580 to 820 nm with a peak of 700 nm was observed at forward bias voltages larger than 18 V.
Abstract: We have fabricated a new type of light‐emitting diode based on a porous silicon and microcrystalline silicon carbide pn junction. The visible light emission from 580 to 820 nm with a peak of 700 nm was observed at forward bias voltages larger than 18 V, and the emission was quite uniform over an area of 1 cm2.

42 citations

Patent
14 Aug 1979
TL;DR: In this article, a clear solution derived from titanium alkoxides, water, alcohol, a suitable acid, and a P or N dopant compound by partial hydrolysis and polymerization is applied to the surface of a silicon chip.
Abstract: The PN juncture in a silicon chip and an oxide coating on its surface are simultaneously formed from clear solution derived from titanium alkoxides, water, alcohol, a suitable acid, and a P or N dopant compound by partial hydrolysis and polymerization. The solution is applied to the surface of a silicon chip. The chip is then heated which converts the solution to a solid oxide coating which meets the antireflective optical film requirements and induces the migration of the dopants into the chip, forming a PN junction in the chip. The method also provides deep and uniform junction formation or diffusion without resulting in excessive carrier concentration.

42 citations

Patent
Reinhard Stengl1
06 May 1991
TL;DR: In this article, a planar pn junction with high electric strength is considered, where a plurality of field plates are separated from a semiconductor zone residing below and extending the semiconductor region by an electrically insulating layer.
Abstract: A planar pn-junction with high electric strength, which separates a semiconductor region inserted in a semiconductor body from the rest of the semiconductor body, has, in its border region, a plurality of field plates which are separated from a semiconductor zone residing below and extending the semiconductor region by an electrically insulating layer. The field plates contact the semiconductor zone in the area of contact holes. The contact holes respectively have set distances between them and the inner and outer field plate edges, whereby below those field plate parts residing between the contact holes and the inner field plates borders, local doping maxima of the semiconductor zone are provided.

42 citations

Patent
25 Mar 2004
TL;DR: In this paper, a thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain, where a cavity is defined below the curved Si layer for reducing a parasitic capacitance due to a pn junction.
Abstract: A high-speed, low-power-consumption semiconductor device has a thin-film Si layer with a source/drain formed therein. The thin-film Si layer is curved from a region directly below a gate electrode toward a region near the source/drain. The curved thin-film Si layer develops strains in a channel region disposed directly below the gate electrode sandwiched by the source/drain in the thin-film Si layer, for thereby increasing a carrier mobility. A cavity is defined below the curved thin-film Si layer for reducing a parasitic capacitance due to a pn junction.

42 citations

Patent
Paul A. Gough1
03 Jun 1992
TL;DR: In this paper, an MOS structure is provided by a fifth region (11) forming a pn junction with the cathode region (9), a sixth region (13) in contact with the C electrode (C), and an insulated gate (15) overlying a conduction channel area (110) of the fifth region(11) for defining a gateable conductive path for charge carriers into the cathodes region(9) to initiate thyristor action.
Abstract: A semiconductor device includes a thyristor (4,5,8,9) in which connection is made to the cathode region (9) of the thyristor by means of an MOS structure. The MOS structure is provided by a fifth region (11) forming a pn junction with the cathode region (9), a sixth region (13) in contact with the cathode electrode (C) and forming a pn junction (14) with the fifth region (11), and an insulated gate (15) overlying a conduction channel area (110) of the fifth region (11) for defining a gateable conductive path for charge carriers into the cathode region (9) to initiate thyristor action. The conductive path is thus controlled by the voltage applied to the insulated gate (15), enabling the flow of charge carriers to the cathode region (9) to be stemmed by application of an appropriate gate voltage oxide. The fifth region (11) is electrically connected to provide a path for extraction of charge carriers during turn-off of the thyristor, thereby improving the controllable current capability of the thyristor.

42 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202237
2021116
2020166
2019251
2018203