p–n junction

About: p–n junction is a research topic. Over the lifetime, 7701 publications have been published within this topic receiving 108890 citations. The topic is also known as: p-n junction.

Method for forming a p-n junction in silicon carbide

Abstract: A method for forming a p-n junction in silicon carbide includes the steps of amorphizing a portion of a monocrystalline silicon carbide substrate, implanting dopant ions into the amorphous portion of the substrate and then recrystallizing the amorphous portion to thereby form a substantially monocrystalline region including the dopant ions. In particular, the amorphizing step includes the steps of masking an area on the face of the monocrystalline silicon carbide substrate and then directing electrically inactive ions to the masked area so that an amorphous region in the substrate is formed. Accordingly, the amorphous region has sidewalls extending to the face that are substantially orthogonal to the bottom edge of the amorphous region. Once the amorphized region is defined, electrically active dopant ions are implanted into the amorphous region. The dopant ions are then diffused into the amorphous region and become uniformly distributed. Next, the doped amorphized region is recrystallized to obtain a substantially monocrystalline doped region. If the region surrounding the recrystallized region are of opposite conductivity type, a vertically walled p-n junction is formed.

Method of fabricating semiconductor device containing dielectrically isolated PN junction for enhanced breakdown characteristics

Abstract: A semiconductor device includes a field shield region that is doped opposite to the conductivity of the substrate and is bounded laterally by dielectric sidewall spacers and from below by a PN junction. For example, in a trench-gated MOSFET the field shield region may be located beneath the trench and may be electrically connected to the source region. When the MOSFET is reverse-biased, depletion regions extend from the dielectric sidewall spacers into the “drift” region, shielding the gate oxide from high electric fields and increasing the avalanche breakdown voltage of the device. This permits the drift region to be more heavily doped and reduces the on-resistance of the device. It also allows the use of a thin, 20 Å gate oxide for a power MOSFET that is to be switched with a 1V signal applied to its gate while being able to block over 30V applied across its drain and source electrodes, for example.

TYPE CONVERSION AND p‐n JUNCTION FORMATION IN ION‐IMPLANTED ZnTe

Abstract: Type conversion and p‐n junction formation, produced by the implantation of 400‐keV F+ ions into p‐type ZnTe, have been confirmed by the thermal probe test, photovoltaic effect, I‐V characteristics, Hall effect, and EPR results.

p--n junction as an ultralinear calculable thermometer

Abstract: A mode of operation of a p--njunction is described which leads to an output voltage linearly related to temperature, independent of device geometry or semiconductor material, and determined only by fundamental physical constants and current.