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p–n junction

About: p–n junction is a research topic. Over the lifetime, 7701 publications have been published within this topic receiving 108890 citations. The topic is also known as: p-n junction.


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24 Aug 2011
TL;DR: In this article, the authors present two emerging industries based on p-n junctions make a significant contribution to the reduction in fossil fuel consumption: solar cells and light emitting diodes (LEDs).
Abstract: Semiconductor devices have made a major impact on the way we work and live. Today semiconductor p-n junction diode devices are experiencing substantial growth: solar cells are used on an unprecedented scale in the renewable energy industry; and light emitting diodes (LEDs) are revolutionizing energy efficient lighting. These two emerging industries based on p-n junctions make a significant contribution to the reduction in fossil fuel consumption.

30 citations

Proceedings ArticleDOI
01 Dec 2018
TL;DR: In this article, homoepitaxial GaN p-n junction diodes with novel beveled-mesa structures were fabricated, which showed the breakdown voltages of 180 −480 V, small leakage currents, and excellent avalanche capabilities.
Abstract: We report homoepitaxial GaN p-n junction diodes with novel beveled-mesa structures. The n-layers and p-layers, the doping concentrations of which are comparable, were prepared. We found that electric field crowding does not occur in the structure using TCAD simulation. The fabricated devices showed the breakdown voltages of 180–480 V, small leakage currents, and excellent avalanche capabilities. The breakdown voltages increased at elevated temperature. At the breakdown, nearly uniform luminescence in the entire p-n junctions was observed in all the devices. These results are strong evidences that the uniform avalanche breakdowns occurred in the devices. We carefully characterized the depletion layer width at the breakdown, and the parallel-plane breakdown electric fields of 2.8-3.5 MV/cm were obtained, which are among the best of the reported non-punch-through GaN vertical devices.

30 citations

Journal ArticleDOI
TL;DR: In this paper, a tin implantation prior to implanting 10 keV boron and then annealing for 30 min at 800 °C results in a 0.22μm-deep p+/n junction.
Abstract: Amorphizing n‐type 〈100〉 silicon by tin implantation prior to implanting 10 keV boron and then annealing for 30 min at 800 °C results in a 0.22‐μm‐deep p+/n junction. The implanted tin prevents boron channeling, enhances the quality of the solid phase epitaxial regrowth of the silicon, and shows no measurable diffusion. A discontinuous band of dislocation loops, 20–30 nm in diameter, with a density below 1010 cm−2 remains at the original amorphous‐crystalline interface after annealing. Junctions are nearly ideal and are characterized at −5 V reverse bias by an areal leakage of −5 nA cm−2 and a peripheral leakage less than −0.1 fA μm−1.

30 citations

Patent
05 May 1980
TL;DR: In this article, an improvement for the electrode structure of the MIS type semiconductor integrated circuit is presented, in which the ohmic contact with the Si substrate is formed on the top of the semiconductor chip, and electrodes which consist of an upper Al layer and a lower polycrystalline Si layer are used for a drain electrode and a source electrode.
Abstract: Disclosed herein is an improvement for the electrode structure of the MIS type semiconductor integrated circuit, in which the ohmic contact with the Si substrate is formed on the top of the semiconductor chip. The electrodes which consist of an upper Al layer and a lower polycrystalline Si layer are used for a drain electrode and a source electrode. These electrodes should be isolated from the substrate by the underlying PN junction. Another electrode, for connecting to the substrate consists of an Al layer directly in contact with the underlying N type region and which is short circuited with the substrate through the N type region due to the alloy formation between the Al and the substrate material. An MIS type semiconductor device with a grounded substrate or with a back gate bias is obtained in a simple structure by the improved source and drain electrode structure.

30 citations

Journal ArticleDOI
TL;DR: The feasibility of a new device structure based on vdWs heterostructures and its potential in future low‐power electronic and optoelectronic device applications is demonstrated.
Abstract: Benefiting from the technique of vertically stacking 2D layered materials (2DLMs), an advanced novel device architecture based on a top-gated MoS2/WSe2 van der Waals (vdWs) heterostructure is designed. By adopting a self-aligned metal screening layer (Pd) to the WSe2 channel, a fixed p-doped state of the WSe2 as well as an independent doping control of the MoS2 channel can be achieved, thus guaranteeing an effective energy-band offset modulation and large through current. In such a device, under specific top-gate voltages, a sharp PN junction forms at the edge of the Pd layer and can be effectively manipulated. By varying top-gate voltages, the device can be operated under both quasi-Esaki diode and unipolar-Zener diode modes with tunable current modulations. A maximum gate-coupling efficiency as high as ≈90% and a subthreshold swing smaller than 60 mV dec-1 can be achieved under the band-to-band tunneling regime. The superiority of the proposed device architecture is also confirmed by comparison with a traditional heterostructure device. This work demonstrates the feasibility of a new device structure based on vdWs heterostructures and its potential in future low-power electronic and optoelectronic device applications.

30 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202237
2021116
2020166
2019251
2018203