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p–n junction

About: p–n junction is a research topic. Over the lifetime, 7701 publications have been published within this topic receiving 108890 citations. The topic is also known as: p-n junction.


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Patent
14 Sep 1978
TL;DR: A photovoltaic semiconductor device is a horizontal multijunction seriesarray solar battery with a monocrystalline body and having elongate zones of aluminum doped silicon passed entirely through N-type silicon layers by Thermomigration process to connect together epitaxially grown buried P layers as mentioned in this paper.
Abstract: A photovoltaic semiconductor device which is a horizontal multijunction series-array solar battery with a monocrystalline body and having elongate zones of aluminum doped silicon passed entirely through N-type silicon layers by Thermomigration process to connect together epitaxially grown buried P layers. Masked elongate N diffusion zones which are parallel and substantially contiguous to each elongated P zone penetrates at least through the lowest P layer thereby forming an inactive pn junction. A thin shallow layer of P-type material is diffused across the top N-type layer. Topologically continuous photovoltaic junctions exist in each cell of the photovoltaic semiconductor device between the shallow layer of P-type material, the buried layer or layers of P-type material, the elongate zone of aluminum doped silicon, and the N-type silicon thereby forming active pn junctions. Metallic strips, at the other pn junctions formed by the thermomigrated aluminum which are inactive, electrically connect the cells together. A method is disclosed for manufacturing the photovoltaic semiconductor device.

27 citations

Patent
Masao Yamada1, Motoo Nakano1, George J. Collins1, Tetsuro Tamura1, Akira Takazawa1 
28 Apr 1993
TL;DR: In this article, an Si or SiC semiconductor layer is subjected to anodic oxidization in an HF solution to form a porous semiconductor layers, which are then dipped in pure water to shorten reaction time and help bubbles separate from the surface of the porous region.
Abstract: An Si or SiC semiconductor layer is subjected to anodic oxidization in an HF solution to form a porous semiconductor layer. Without drying the porous semiconductor layer, it is then dipped in pure water. Ultrasonic waves applied to the pure water shorten the reaction time and help bubbles separate from the surface of the porous region. The porous semiconductor layer is used for forming a pn junction, and carriers are injected into the pn junction.

27 citations

Patent
01 Dec 1975
TL;DR: In this article, a light-emitting diode element comprises a semiconductor wafer including a pair of a p-type semiconductor region and an n-type region forming a pn junction.
Abstract: A light-emitting diode element comprises a semiconductor wafer including a pair of a p-type semiconductor region and an n-type semiconductor region forming a pn junction, an inclined first electrode provided on at least one of the peripheral edges of the surface of one of the semiconductor regions in the semiconductor wafer, and a flat second electrode provided on the surface of the other semiconductor region. A light-emitting diode device is provided in which a plurality of such light-emitting diode elements are respectively received in a plurality of openings of a substrate having a first wiring conductor group and a second wiring conductor group electrically connected to the first and second electrodes respectively of the light-emitting diode elements by a low-melting metal. Thus, these light-emitting diode elements can be mounted on the single substrate in a high package density, and the light-emitting diode device of simple construction can be easily assembled.

27 citations

Journal ArticleDOI
TL;DR: In this paper, integrated, silicon single-nanowire diodes were reported, which used atmospheric-pressure chemical vapor deposition, used SiCl4 diluted in H2 on (100) n-type silicon substrates.
Abstract: We report on integrated, silicon single-nanowire diodes. Gold catalyst templates, defined by lithography, controlled the location of nanowires grown with a vapor-liquid-solid mechanism. The nanowire growth, by atmospheric-pressure chemical vapor deposition, used SiCl4 diluted in H2 on (100) n-type silicon substrates. Postgrowth oxidation and wet etching reduced the nanowire diameters and removed unintentional small diameter nanowires. Spin-on glass isolated the nanowire tips from the substrate, which were then contacted with aluminum. Current-voltage measurements show rectification and ideality factors consistent with pn junction diodes. However, the gold catalyzed nanowires have much higher than expected hole concentrations that cannot be explained by behaviors reported for gold diffused into silicon.

27 citations

Patent
24 Mar 1969
TL;DR: In this article, an integrated circuit variable coupler utilizing metal oxide semiconductor (MOS) techniques is described, where the degree of coupling or capacitance of the coupler is a function of the size of the depletion region of a PN junction which can be varied by a voltage applied across a thin film resistor deposited on an oxide layer.
Abstract: Described is an integrated circuit variable coupler utilizing metal oxide semiconductor (MOS) techniques, wherein the degree of coupling or capacitance of the coupler is a function of the size of the depletion region of a PN junction which can be varied by a voltage applied across a thin film resistor deposited on an oxide layer.

27 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202237
2021116
2020166
2019251
2018203