p–n junction

About: p–n junction is a research topic. Over the lifetime, 7701 publications have been published within this topic receiving 108890 citations. The topic is also known as: p-n junction.

Flexible Transparent Field‐Effect Diodes Fabricated at Low‐Temperature with All‐Oxide Materials

Abstract: DOI: 10.1002/aelm.201500486 of our knowledge, the first flexible and fully transparent fieldeffect diode (FED) fabricated at low-temperature with all oxide materials, using diode-connected thin-film transistor architecture. Conventional thin-film transistors were also fabricated at the same time as reference. The diodes exhibited a high rectification ratio of 5 × 108 and low leakage current of 1 pA, same as the on/off ratio and off current in the referenced TFT. Technology computer aided design (TCAD) simulation was employed to explore its working mechanism. Finally, a singlestage rectifier was demonstrated by applying this unique FED to rectify alternating current (AC) signals with different amplitudes and frequencies. For ease of understanding, a conceptualized schematic of FED is shown in Figure 1a. The device is two-terminal contacted, with dielectric and channel layers stacked inside. A lowtemperature (≤100 °C) process (Figure 1b) was used to fabricate the devices. (Details of the fabrication process can be found in Experimental Section.) During the same process, a conventional TFT was fabricated as well to serve as reference (see the top view in Figure 1c). Both of the devices on polyethylene naphthalate (PEN) and glass substrates are optically transparent, with the whole devices (including the substrates) exhibiting a transmittance over 80% in full visible spectral range (Figure 1d). The referenced TFT adopted a staggered bottom-gate structure, with channel width/length (W/L) of 300/20 μm. Figure 2a shows the transfer characteristics of referenced TFT on PEN substrates (IDS–VGS, DS denotes drain to source and GS gate to source). An on/off current ratio of 5 × 108 was obtained by operating the TFT at VDS = 3 V and VGS = ±20 V. The fieldeffect mobility (μeff) of 11.56 cm2 V−1 s−1 was calculated from the linear region. The SS was determined to be 0.53 V dec−1, calculated using the minimum value of 1/(∂log(IDS)/∂VGS) versus VGS plot. The turn-on voltage (VON) was read out to be ≈0 V from the transfer curve. Gate oxide capacitance (Cox) of 1.5 × 10−7 F cm−2 was extracted from capacitance–voltage (C–V) measurement curve (not shown here). Figure 2b shows the IDS–VDS output characteristics at VGS = 5–10 V, which exhibits typical square-law behavior. It should be noted that good ohmic contact was formed at the interface of indium tin oxide/zinc oxide (ITO/ZnO), so no rectifying property was expected from source and drain contacts. These properties in referenced TFT are important, as the field-effect diode has the identical material quality and will follow the same field-effect principles. Devices on glass substrates have similar characteristics with those on PEN, so, to avoid repetition, the electrical characteristics in this paper are all carried out on the PEN devices. Figure 2c shows the current–voltage (I–V) characteristics of FED in flat and bent states, respectively (see Figure 2d). A high rectification ratio of 5 × 108 was obtained at V = ±20 V, which is much higher than most of the reported Schottky and pn junction Flexible and transparent electronics[1–3] have gained momentum in the last decade, owing to their great potential in future technological applications.[4–6] Most of the researches, concerning about inorganic semiconductors, have been generally involved in metal oxide semiconductors, as they are optically transparent and compatible with low temperature process. Flexible and transparent oxide thin-film transistors (TFTs), as key devices for realizing next generation circuits, have been extensively studied both on glass and plastic substrates during these years.[7–9] High performances with field-effect mobility more than 10 cm2 V−1 s−1, on/off current ratio more than 108, and subthreshold swing (SS) less than 0.5 V dec−1 were obtained.[7–9] Besides TFTs, thin-film diodes (TFDs) are important components to achieve electronic circuits, especially for energy conversion[10,11] and selective switching.[12,13] However, few researches have focused on flexible or transparent diodes. The limited reports can be categorized into 4 types: (1) pn heterojunction diode.[14–19] As most of the widebandgap semiconductors are n-type conductive, a proper p-type wide-bandgap material must be chosen wisely to form a large built-in potential barrier. (2) Schottky junction diode.[20–23] The electron affinities (χ) of most wide-bandgap materials are more than 4 eV, thus only a small Schottky barrier height could be formed with non-noble metals. (3) Metal-insulatesemiconductor diode.[24] As in Schottky diode, a large difference between metal work function (ΦM) and semiconductor affinity (χ) is needed to achieve a large rectification ratio. (4) Metal-insulator-metal (MIM) diode.[25,26] Actually, it is not easy for MIM diodes to be applied in transparent circuits because of the difficulties to find two kinds of transparent electrodes with large work function difference. (5) Self-switching diode.[27] Besides small rectification ratio, this kind of device involves nanofabrication, which may bring high costs and challenges in technology compatibility. Diode-connected field-effect transistor/bipolar junction transistor, with drain/collector and gate/base electrodes shorted, is widely used in integrated circuits to serve as passive load.[28] Because of its asymmetric current–voltage characteristics,[29,30] diode-connected transistor is also used as rectification device in energy harvest systems.[31,32] This paper reports, to the best www.MaterialsViews.com www.advelectronicmat.de

Realization of radial p-n junction silicon nanowire solar cell based on low-temperature and shallow phosphorus doping.

Abstract: A radial p-n junction solar cell based on vertically free-standing silicon nanowire (SiNW) array is realized using a novel low-temperature and shallow phosphorus doping technique. The SiNW arrays with excellent light trapping property were fabricated by metal-assisted chemical etching technique. The shallow phosphorus doping process was carried out in a hot wire chemical vapor disposition chamber with a low substrate temperature of 250°C and H2-diluted PH3 as the doping gas. Auger electron spectroscopy and Hall effect measurements prove the formation of a shallow p-n junction with P atom surface concentration of above 1020 cm−3 and a junction depth of less than 10 nm. A short circuit current density of 37.13 mA/cm2 is achieved for the radial p-n junction SiNW solar cell, which is enhanced by 7.75% compared with the axial p-n junction SiNW solar cell. The quantum efficiency spectra show that radial transport based on the shallow phosphorus doping of SiNW array improves the carrier collection property and then enhances the blue wavelength region response. The novel shallow doping technique provides great potential in the fabrication of high-efficiency SiNW solar cells.

Effect of the pn junction engineering on Si microwire-array solar cells

Abstract: We report on the impact of the doping concentration design on the performance of silicon microwire arrays as photovoltaic devices. We have fabricated arrays with different p- and n-doping profiles and thicknesses, obtaining mean efficiencies as high as 9.7% under AM 1.5G solar illumination. The results reveal the importance of scaling the microwire diameter with the depletion width resulting from doping concentrations. The doping of the core should be kept low in order to reduce bulk recombination. Furthermore, the thickness of the n-shell should be kept as thin as possible to limit the emitter losses.

Nonvolatile memory cell with P-N junction formed in polysilicon floating gate

Abstract: An integrated circuit memory cell (10) is formed with a P-N junction polycrystalline floating gate (13) with a lightly boron doped on the source side (13B) and a heavily arsenic or phosphorous doped on the drain side (13A) plus the channel region (Ch) . The cells (10) are formed in an array at a face of a semiconductor body (22), each cell including a source (11) and including a drain (12). An improved over-erase characteristic is achieved by forming a P-N junction (JU) in the floating gate (13). Use of a P-N junction (JU) in polycrystalline floating gate (13) prevents the cell (10) from going into depletion, causes a tighter distribution of erased threshold voltages VT, and improves device life because fewer electrons travel through the gate oxide (30).