p–n junction

About: p–n junction is a research topic. Over the lifetime, 7701 publications have been published within this topic receiving 108890 citations. The topic is also known as: p-n junction.

A ballistic pn junction in suspended graphene with split bottom gates

Abstract: We have developed a process to fabricate suspended graphene devices with local bottom gates, and tested it by realizing electrostatically controlled pn junctions on a suspended graphene mono-layer nearly 2 μm long. Measurements as a function of gate voltage, magnetic field, bias, and temperature exhibit characteristic Fabry-Perot oscillations in the cavities formed by the pn junction and each of the contacts, with transport occurring in ballistic regime. Our results demonstrate the possibility to achieve a high degree of control on the local electronic properties of ultra-clean suspended graphene layers, a key aspect for the realization of high quality graphene nanostructures.

Product wafer junction leakage measurement using corona and a kelvin probe

Abstract: Corona charge is applied to a semiconductor product wafer to reverse bias PN junctions. Measurements of voltage decay in the dark and in the light are made and combined to determine a PN junction leakage characteristic. A portion of the dark measurement is taken in the light to permit normalizing the light and dark measurements.

Junction field-effect transistor controlled by merged depletion regions

Abstract: A new method of semiconductor operation has been conceived, developed and applied to produce a revolutionary new semiconductor design. The method is that of merging depletion regions for purposes of operation, isolation and control of channel current in a junction field-effect transistor. Using this method depletion regions are made to merge with suitable biasing in an intervening layer interposed between the gate and channel of a junction field-effect device and the interaction of the depletion regions is used for isolation and coupling to alter the associated depletion region in the channel of the junction field-effect device. A number of embodiments are disclosed of the new junction field-effect transistor controlled by merged depletion regions. In each embodiment a channel of one conductivity type material is formed in a semiconductor body of opposite type material. A gate region of the same conductivity type material as the channel is placed near enough to the channel so that when the gate junction is reversed bias, the gate depletion region merges with the channel junction depletion region in the intervening layer. When the two depletion regions have merged, the gate controls the channel current in a manner similar to conventional devices. Because the output and input and control connections are of the same conductivity type material, no metal contacts or interconnections are required. The lack of need for metal interconnects makes the device better suited to integrated circuits than any other device. In addition, the depletion regions surrounding the gate and channel isolate the gate and channel from other semiconductor regions of the same conductivity type and thus isolation regions are not required for the junction field-effect transistor controlled by mergers depletion regions. Consequently, use of the invention can result in the densest form of logic available today. Such devices hold the promise of improved performance in almost every semiconductor device application and can be used in almost every application where MOS and junction field-effect devices are now used.