Topic
p–n junction
About: p–n junction is a research topic. Over the lifetime, 7701 publications have been published within this topic receiving 108890 citations. The topic is also known as: p-n junction.
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TL;DR: In this article, the authors reported the first experimental measurements of stable positive temperature coefficient behavior observed in 4H-SiC pn junction rectifiers, which is presently the best-suited SiC polytype for power device implementation.
Abstract: It has been suggested that once silicon carbide (SiC) technology overcomes some crystal growth obstacles, superior SiC semiconductor devices would supplant silicon in many high-power applications. However, the property of positive temperature coefficient of breakdown voltage, a behavior crucial to realizing excellent power device reliability, has not been observed in 4H-SiC, which is presently the best-suited SiC polytype for power device implementation. This paper reports the first experimental measurements of stable positive temperature coefficient behavior observed in 4H-SiC pn junction rectifiers. This research indicates that robust 4H-SiC power devices with high breakdown reliability should be achievable after SiC foundries reduce material defects such as micropipes, dislocations, and deep level impurities.
68 citations
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21 Dec 2001
TL;DR: In this article, the authors proposed a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element.
Abstract: In the semiconductor integrated circuit device, a first P + type buried layer formed as an anode region and an N + type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element and in which a withstand voltage can be maintained by a depletion layer thus formed to prevent breakdown of elements in the device attributable to a breakdown current.
68 citations
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21 May 2009
TL;DR: In this article, a static random access memory circuit with a first horizontally oriented transistor and an interconnect region which includes a conductive line is presented. But the circuit is not suitable for the use of a single-input single-output (SISO) memory.
Abstract: A bonded semiconductor structure static random access memory circuit includes a support substrate which carries a first horizontally oriented transistor, and an interconnect region which includes a conductive line. The memory circuit includes a donor substrate which includes a semiconductor layer stack coupled to a donor substrate body region through a detach region, wherein the semiconductor layer stack is coupled to the interconnect region through a bonding interface, and wherein the semiconductor layer stack includes a pn junction.
68 citations
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17 Apr 1995TL;DR: In this paper, a gate electrode is formed through a gate insulating film on a channel region between the source and drain layers to induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer.
Abstract: A high-resistant p-silicon layer is formed on a silicon substrate through a silicon oxide film. N-source and n-drain layers are selectively formed in the surface of the high-resistant p-silicon layer. A gate electrode is formed through a gate insulating film on a channel region between the source and drain layers. To induce an n-inverted layer under the gate electrode, a p-base layer is formed in the high-resistant p-silicon layer. A depletion layer extending from a pn junction between the n-drain layer and the high-resistant p-silicon layer reaches the silicon oxide film in a thermal equilibrium state. Part of the high-resistant p-silicon layer extends into a channel region between the drain and base layers. The drain and base layers are connected to each other through part of the depletion layer in the thermal equilibrium state. A field effect transistor having a high-speed operation is provided.
67 citations
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TL;DR: In this paper, a cubic GaN p-n diode has been grown on n-type GaAs (001) substrates by plasma assisted molecular epitaxy, and the optical properties are characterized by photoluminescence at room temperature and 2 K.
Abstract: A cubic GaN p–n diode has been grown on n-type GaAs (001) substrates by plasma assisted molecular epitaxy. For p- and n-type doping, elemental Mg and Si beams have been used, respectively. The optical properties are characterized by photoluminescence at room temperature and 2 K. Current–voltage and capacitance–voltage measurements of the cubic GaN n+–p junction are performed at room temperature. The electroluminescence at 300 K is measured through a semitransparent Au contact. A peak emission at 3.2 eV with a full width at half maximum as narrow as 150 meV is observed, indicating that near-band edge transitions are the dominating recombination processes in our device. A linear increase of the electroluminescence intensity with increasing current density is measured.
67 citations