p–n junction

About: p–n junction is a research topic. Over the lifetime, 7701 publications have been published within this topic receiving 108890 citations. The topic is also known as: p-n junction.

Quantification of scanning capacitance microscopy imaging of the pn junction through electrical simulation

Abstract: Determining the cross-sectional doping profile of very small metal–oxide–semiconductor field effect transistors and specifically the direct measurement of their channel length is necessary for true channel engineering to be possible. Scanning capacitance microscopy (SCM) has generated unprecedented images of the cross-sectional doping profiles of very small transistors. The bias voltage dependence of these images has motivated us to investigate the SCM technique in greater detail. Using electrical simulations, we have focused on the pn junction to establish the qualitative and quantitative relationship between the bias voltage and the pn junction location. The ability to confidently interpret the images produced with SCM will allow us to improve simulation models, trouble-shoot process flow, and determine the effective channel length of semiconductor devices.

Semiconductor laser apparatus and manufacturing method thereof

Abstract: A semiconductor laser apparatus includes a substrate, a vertical-cavity surface-emitting semiconductor laser diode (VCSEL) including a first and second mirror layers of a first and second conduction types, respectively, an active region between the first and second mirror layers, a first and second electrode layers electrically connected with the first and second mirror layers, respectively, and at least one Zener diode including a first and second semiconductor regions of a first and second conduction types, respectively, and a third and fourth electrode layers electrically connected with the first and second semiconductor regions, respectively. The second semiconductor region is formed in a portion of the first semiconductor region and forms a PN junction with the first semiconductor region. The VCSEL and the Zener diode are formed on the substrate. The first and second electrode layers are electrically connected with the fourth and third electrode layers, respectively.

Integrated semiconductor light emitting element with oscillation wavelength and phase modulated light output

Abstract: A semiconductor light emitting element is disclosed, which is provided with a light emitting region having a diffraction grating formed by periodic corrugations, a modulation region having an external waveguide layer optically connected directly to the light emitting region and a pn junction separated from a pn junction of the light emitting region and a window region formed of a semiconductor having a larger energy gap than that of a light emitting layer of the light emitting region and extending from at least one end of the light emitting region and the external waveguide layer. The refractive index of the external waveguide is varied through utilization of the electrooptic effect so that the frequency or phase of light stably oscillating at a single wavelength is precisely controlled or modulated. In particular, when the window region is formed only outside the light emitting region, frequency modulation is carried out, and when the window region is formed at least outside the modulation region, phase modulation takes place.

Capacitive memory having a PN junction writing and tunneling through an insulator of a charge holding electrode

Abstract: A semiconductor memory device whose data hold condition is not affected due to degradation of transistor characteristics by minimizing leakage charges and the switching transistor size. The semiconductor memory device employs memory cell charge holding electrode that is insulated from the remaining memory cell structure, particularly the switching transistor source drain leakage path. The write element controls the tunneling of charge carriers through such insulator to the charge holding portion or capacitor electrode, for writing data. Particularly, the write element includes a PN junction for various advantages.

A methodology for experimentally based determination of gap shrinkage and effective lifetimes in the emitter and base of p-n junction solar cells and other p-n junction devices

Abstract: An experimentally based methodology is described that determines the effective gap shrinkage and lifetime in the emitter of a p-n junction solar cell. It provides the first experimental means available for assessing the importance of gap shrinkage relative to that of large recombination rates in the highly doped emitter. As an additional result of the procedures employed, the base lifetime is also determined. The methodology pertains to a solar cell after the junction is formed. Hence each material parameter determined includes the effects of the processing used in junction fabrication. The methodology consists of strategy and procedures for designing experiments and interpreting data consistently with the physical mechanisms governing device behavior. This careful linking to the device physics uncovers the material parameters concealed in the data. To illustrate the procedures, they are applied to an n+-p solar cell having substrate resistivity of about 0.1 Ω cm.