p–n junction

About: p–n junction is a research topic. Over the lifetime, 7701 publications have been published within this topic receiving 108890 citations. The topic is also known as: p-n junction.

Analysis of the electrical properties of Cr/n-BaSi2 Schottky junction and n-BaSi2/p-Si heterojunction diodes for solar cell applications

Abstract: Current status and future prospects towards BaSi2 pn junction solar cells are presented. As a preliminary step toward the formation of BaSi2 homojunction diodes, diodes with a Cr/n-BaSi2 Schottky junction and an n-BaSi2/p-Si hetero-junction have been fabricated to investigate the electrical properties of the n-BaSi2. Clear rectifying properties were observed in the current density versus voltage characteristics in both diodes. From the capacitance-voltage measurements, the build-in potential, VD, was 0.53 V in the Cr/n-BaSi2 Schottky junction diode, and the Schottky barrier height was 0.73 eV calculated from the thermoionic emission theory; the VD was about 1.5 V in the n-BaSi2/p-Si hetero-junction diode, which was consistent with the difference in the Fermi level between the n-BaSi2 and the p-Si.

Improved High Efficiency Stacked Microstructured Neutron Detectors Backfilled With Nanoparticle $^{6}$ LiF

Abstract: Silicon diodes with large aspect ratio trenched microstructures, backfilled with 6LiF, show a dramatic increase in thermal neutron detection efficiency beyond that of conventional thin-film coated planar devices. Described in this work are advancements in the technology using detector stacking methods to increase thermal neutron detection efficiency, along with the current process to backfill 6LiF into the silicon microstructures. The highest detection efficiency realized thus far is over 42% intrinsic thermal neutron detection efficiency by device-stacking methods. The detectors operate as conformally diffused pn junction diodes each having 1 cm2 area. Two individual devices were mounted back-to-back with counting electronics coupling the detectors together into a single dual-detector device. The solid-state silicon device was operated at 3 V and utilized simple signal amplification and counting electronic components that have been adjusted from previous work for slow charge integration time. The intrinsic detection efficiency for normal-incident 0.0253 eV neutrons was found by calibrating against a 3He proportional counter.

Arsenic cluster dynamics in doped GaAs

Abstract: We have studied the formation of As precipitates in doped GaAs structures that were grown by molecular beam epitaxy at low substrate temperatures and subsequently annealed. We find that the As precipitates form preferentially on the n side of such fabricated GaAs pn junctions. As the coarsening process proceeds, there is a gradual increase in the amount of As in precipitates in the n‐GaAs region and a decrease in the p‐GaAs region; the depletion region between the pn junction becomes free of As precipitates. These observations can be understood qualitatively based on the charge states of the As interstitial and using thermodynamic arguments in which the crystal attempts to minimize the chemical potential during the anneal. The presence of the excess As results in a stable Be profile even to anneals of 950 °C. Finally, a temperature cycling technique to grow arbitrarily thick GaAs epilayers containing As precipitates was demonstrated.

Insulated gate field-effect transistor and a method of manufacturing the same

Abstract: The invention aims at precisely making an effective junction depth sufficiently small with respect to a substrate surface having a steep PN junction stable in its configuration and having a channel formed therein in relation to an extension portion. Gate electrodes are formed on a P-type well and an N-type well through respective gate insulating films. Two extension portions are formed from two first epitaxial growth layers which contact regions, of the P-type well and the N-type well, where channels are to be formed, respectively, and which are at a distance from each other. Two second epitaxial growth layers are formed on the first epitaxial growth layers in positions which are further at a distance from facing ends of the two extension portions in a direction of being separate from each other. Thus, two source/drain regions are formed on a PMOS side and on an NMOS side each. In the case of this structure, there is adopted no ion implantation for introducing impurities into a deep portion. Hence, the impurities in the extension portions do not thermally diffuse into the substrate side through the activation anneal.