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Page layout

About: Page layout is a research topic. Over the lifetime, 2266 publications have been published within this topic receiving 23261 citations.


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Patent
03 Apr 2013
TL;DR: In this article, an android equipment-based dynamic wallpaper arrangement method was proposed to arrange a specified game page layout as a wallpaper, and the view with the transparent property covers the wallpaper, so that the game web layout can be continuously refreshed to be a dynamic wallpaper.
Abstract: The invention relates to an android equipment-based dynamic wallpaper arrangement method, an android equipment-based dynamic wallpaper arrangement device, and a terminal. The method comprises the following steps: A, associating a specified game page layout and a preset trigger key; B, responding an action instruction of the preset trigger key and entering the specified game page layout; and C, initializing view with transparent property, and covering the view on the game web layout, and initializing and displaying an application icon on the view with the transparent property. According to the invention, the specified game page layout is arranged as a wallpaper, the view with the transparent property covers the wallpaper, and the game web layout is visible, so that the game web layout can be continuously refreshed to be a dynamic wallpaper; and the wallpaper can be continuously refreshed along with the development of games, as a result, the type of the wallpaper is more abundant, and user experience is greatly improved.

7 citations

Proceedings ArticleDOI
14 Jul 2011
TL;DR: A web-based environment along with an interactive interface for VLSI schematic design, simulation, and layout design and along with teaching schematics and layouts of circuits, this virtual lab also consists of some experiment explaining about SPICE coding, VHDL and Verilog coding.
Abstract: We present a web-based environment along with an interactive interface for VLSI schematic design, simulation, and layout design. It consist of 10 experiments starting from transistor level design of inverter, then some basic gates such as NAND, NOR, XOR etc, finally design of D latch and flip flop. In each experiment student will learn how to design VLSI circuits both schematic and layout. It also consists of experiment components such as objective, introduction, quiz, and theory etc. which gives step by step explanation of each experiment. It is a powerful self learning supplement for the VLSI design course offered in undergraduate engineering program. Along with teaching schematics and layouts of circuits, this virtual lab also consists of some experiment explaining about SPICE coding, VHDL and Verilog coding. An interactive panel is given in which student will write programming codes, simulate and see real time waveforms. The web based schematic and layout editor is designed to maintain the commonality with EDA tools such as Cadence Virtuoso, HSpice Cosmos, Tanner tools etc.

7 citations

01 Jan 1990
TL;DR: The idea of a Maximal Spanning Arborescence borrowed from Graph Theory constitutes the heart of this method, which allows the layout and handling capabilities of the manufacturing system to minimize the number of machines which must be duplicated within or among several cells.
Abstract: The traditional approach to the implementation of Group Technology cells requires that an independent cell be designed for each part family. This creates the problem of deciding the integer number of each shared machine type that must be assigned to each cell. Usually, either the machines in each cell experience overloading or have underutilized capacity. Nor do any of the methods address the issue of stable cell compositions over multiple production periods. It is difficult to develop a method having the ability to integrate the five subproblems of machine grouping, intracell layout, intercell layout, machine sharing and approximate handling system configuration. This dissertation ignores part family formation because it creates a machine sharing problem. It recognizes that, in the case of machine sharing among part families, methods which do not work with flow data will prove ineffective. The reason is that such data alone can model the layout design and material handling alternatives to machine duplication among cells. Hence, instead of the standard binary machine-part matrix, the proposed method uses the flow characteristics captured in a Travel Chart as input data. This allows the five previously mentioned subproblems to be addressed together. This allows the layout and handling capabilities of the manufacturing system to minimize the number of machines which must be duplicated within or among several cells. The machine groups can be "virtual," i.e. parts from several families can be loaded on a particular machine shared by several cells. This allows identical machines to be placed in a functional layout for production flexibility. An analysis of the overall complexity of the problem suggested necessary simplifications in the method. The proposed method consists of two phases. Phase I is a linear programming problem and Phase 2 is a quadratic programming problem solved using 0-1 integer programming. The idea of a Maximal Spanning Arborescence borrowed from Graph Theory constitutes the heart of this method. Concepts from related areas such as Facilities Design and Cluster Analysis have also been used. Several examples were solved to show the validity of this method.

7 citations

Proceedings ArticleDOI
06 Jun 2013
TL;DR: This work proposes to combine the formalism with computational intelligence methods and apply to the 3D layout problem which require efficient search of large and discontinuous spaces.
Abstract: Shape grammars are generative systems dedicated to specific needs of designers. In the last few years, they have received increased interest especially in building reconstruction and building model generation. We propose to combine the formalism with computational intelligence methods and apply to the 3D layout problem which require efficient search of large and discontinuous spaces. The approach is illustrated by the example of a designing 3D ICs layouts. The presented results have been generated with a use of a dedicated application PerfectShape.

7 citations

Journal ArticleDOI
TL;DR: To validate the proposed algorithm, the layout design of one-space station is formulated as a multi-disciplinary design problem, the developed algorithm is programmed and executed, and the result is compared with those from other two algorithms; it has illustrated the superior performance of the proposed EGEA-TSD.
Abstract: The layout of a space station should be designed in such a way that different equipment and instruments are placed for the station as a whole to achieve the best overall performance. The station layout design is a typical nondeterministic polynomial problem. In particular, how to manage the design complexity to achieve an acceptable solution within a reasonable timeframe poses a great challenge. In this article, a new evolutionary algorithm has been proposed to meet such a challenge. It is called as the expert-guided evolutionary algorithm with a tree-like structure decomposition EGEA-TSD. Two innovations in EGEA-TSD are i to deal with the design complexity, the entire design space is divided into subspaces with a tree-like structure; it reduces the computation and facilitates experts’ involvement in the solving process. ii A human–intervention interface is developed to allow experts’ involvement in avoiding local optimums and accelerating convergence. To validate the proposed algorithm, the layout design of one-space station is formulated as a multi-disciplinary design problem, the developed algorithm is programmed and executed, and the result is compared with those from other two algorithms; it has illustrated the superior performance of the proposed EGEA-TSD.

7 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202325
202273
202165
202093
2019124
201893