Page layout

About: Page layout is a research topic. Over the lifetime, 2266 publications have been published within this topic receiving 23261 citations.

An Automated and Fast OPC Algorithm for OPC-Aware Layout Design

Abstract: To reduce design spin time, OPC-unfriendly spots in IC layout should be found out by designer before tape-out. This can be done by firstly running a "trial OPC" step on the layout, followed by running an OPC step to verify the result. In this paper we introduce a new OPC algorithm using an edge bias modeling method. When given a piece of sample post-OPC layout, software based on this algorithm can automatically correct a design with similar recipe but dozens of times faster than traditional model-based method, at cost of some accuracy loss. This makes the algorithm a good choice for "trial OPC"

Net list generating method and layout designing method of semiconductor integrated circuit

Abstract: A placement 103 of a macrocell is applied to a net list 102 formed by the logic synthesis by using the automatic layout tool, physical information of the macrocell is extracted in a physical information extracting step 104, and a net list 106 including the physical information is generated by attaching the extracted physical information to the instance name of the macrocell. Since the physical information such as placement coordinate, utilization factor, voltage drop value, and the like are attached to the instance name of the macrocell, the physical information can be grasped without reference to the layout data, and also analysis of the simulation and correction of the layout data can be facilitated. Also, since the placement position designation constraint is generated from the net list including the physical information, the high-quality layout design can be carried out.

Print control apparatus and method for page layout preparation

Abstract: Provided are a print layout device, a print layout method and a storage medium therefor with which all data can always be printed by ensuring that data to be printed do not extend out beyond the limits of a printable area, as may occur when the conventional margin setting process is used, with which a margin can be set by employing an additional special print method, such as an N-up print method, and with which a binding margin can be set for bookbinding. In addition, provided is a configuration for implementing those apparatuses and devices without modifying the conventional portions. A host computer comprises a despooler, which calculates a printable area using margin parameters set by a user, enlarges/reduces print data in consonance with the obtained printable area, performs a layout for the resultant data to be printed and margins on a sheet, and prints the data using that layout. The despooler outputs prepared drawing data to a graphic engine to provide a printer driver in a conventional manner.

Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips

Abstract: An EQUATE property is introduced into the layout cell data for a layout design to identify the schematic to which the layout design corresponds. Rather than exploding the layout cell up to the next level for flat checking because the equivalent schematic is not known, the layout cell instances may then be checked hierarchically, with one instance checked internally for compliance with design rules and the like while the remaining instances are merely checked for proper connection to neighboring cells. New layout cell designs may therefore be created as the need arises during layout without requiring schematic checking tools to be rerun.