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Page layout

About: Page layout is a research topic. Over the lifetime, 2266 publications have been published within this topic receiving 23261 citations.


Papers
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Journal ArticleDOI
01 May 2019
TL;DR: The floor plan of an office building in the Netherlands is used as reference, and eleven space layouts based on the reference are proposed, and the result shows that the heating demand of the worst layout is 12% higher than the best layout.
Abstract: Space layout design is one of the most important phases in architectural design, and current studies have shown that it can affect building energy performance. However, its influence has not been quantified. This paper aims at investigating the impact of space layouts on building energy performance. We use the floor plan of an office building in the Netherlands as reference, and propose eleven space layouts based on the reference. Calculations are performed with the tools Honeybee and Ladybug in Grasshopper, which are developed based on Daysim and EnergyPlus, to simulate lighting, cooling and heating demand of these layouts. In addition, we couple daylight with thermal simulation, by importing the artificial lighting schedule calculated in Daysim to EnergyPlus. The result shows that the heating demand of the worst layout is 12% higher than the best layout, the cooling demand of the worst layout is 10% higher than the best layout, and the lighting demand of the worst layout is 65% higher than the best layout. The total final energy use of the worst layout is 19% higher than the best layout.

4 citations

Patent
27 Jun 2007
TL;DR: In this paper, the furniture controller is composed of processor, memory, input/output device, layout design module, information management module, and mobile control module, which is used to move furniture to pointed layout position.
Abstract: The furniture controller is composed of processor, memory, input/output device, layout design module, information management module, and mobile control module. The invention includes steps: first, using information management module to input information of furniture, and layout information of house space; using layout design module to design layout position of furniture, and save result after scheme is designed; finally, mobile control module controls and moves layout positions of furniture based on result designed by the design module. Using effect map for previewing furniture, the invention reaches purpose of satisfying users, and avoiding duplication of labor. Moreover, using modernizes technique to move furniture to pointed layout position, the invention saves time and body force for users, as well as reduces possibility of damaging furniture effectively when moving furniture.

4 citations

Proceedings ArticleDOI
22 Mar 1996
TL;DR: A page layout segmentation algorithm for locating text, background and halftone areas is presented and a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.
Abstract: A page layout segmentation algorithm for locating text, background and halftone areas is presented. The algorithm has been implemented on Splash 2-an FPGA-based array processor. The speed as determined by the Xilinx synthesis tools projects an application speed of 5 MHz. For documents of size 1,024/spl times/1,024 pixels, a significant speedup of two orders of magnitude compared to a SparcStation 20 has been achieved.

4 citations

Patent
04 Oct 2007
TL;DR: In this article, a hierarchical design method and device solving such the problem in hierarchical design that the total optimality of a result is lost due to problem division without deteriorating the advantage of the hierarchical design, that a designing time can be shortened with less memory.
Abstract: PROBLEM TO BE SOLVED: To provide a hierarchical design method and device solving such the problem in hierarchical design that the total optimality of a result is lost due to problem division without deteriorating the advantage of the hierarchical design that a designing time can be shortened with less memory SOLUTION: After arranging a gate level of a chip or wiring, one or a plurality of arbitrary layout areas on the chip are cut out and each of the cut-out areas is blocked, each of the cut-out blocks is redesigned, and design of the blocked area is replaced with a result of the redesigning to change a layout design of the chip COPYRIGHT: (C)2008,JPO&INPIT

4 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202325
202273
202165
202093
2019124
201893