Page layout

About: Page layout is a research topic. Over the lifetime, 2266 publications have been published within this topic receiving 23261 citations.

An elitist strategy genetic algorithm using simulated annealing algorithm as local search for facility layout design

Abstract: A well-planned arrangement of manufacturing departments on a two-dimensional planar region considerably increases the efficiency of its production systems, which is termed facility layout problem (FLP). Conventional layout design approach often designs intercell layout (determining exact location of each department on shop floor area) and flow path layout design of material handling system (MHS) step by step in a sequential manner. This results in suboptimal solutions for FLP. In this paper, an integrated approach is adopted to design the intercell layout and the flow path layout of MHS simultaneously. The quality of the final layout is evaluated by minimizing total material handling cost. Sequence pair (SP) representation is used for layout encoding. The translation from SP to layout is efficiently made by longest common subsequence (LCS) methodology. An elitist strategy genetic algorithm using simulated annealing (E-GASAA) as a local search mechanism is developed and tested with four test problem instances available in the literature. Elitist strategy is incorporated to enhance convergence characteristic of the proposed algorithm. It is found that the proposed E-GASAA is able to produce best solutions consistently for the test problem instance of different sizes within acceptable computational effort. In addition to that, we tried to reduce the computational load with the help of adopted LCS computation methodology and achieved a good improvement.

Optimal column layout for hybrid workloads

Abstract: Data-intensive analytical applications need to support both efficient reads and writes. However, what is usually a good data layout for an update-heavy workload, is not well-suited for a read-mostly one and vice versa. Modern analytical data systems rely on columnar layouts and employ delta stores to inject new data and updates.We show that for hybrid workloads we can achieve close to one order of magnitude better performance by tailoring the column layout design to the data and query workload. Our approach navigates the possible design space of the physical layout: it organizes each column's data by determining the number of partitions, their corresponding sizes and ranges, and the amount of buffer space and how it is allocated. We frame these design decisions as an optimization problem that, given workload knowledge and performance requirements, provides an optimal physical layout for the workload at hand. To evaluate this work, we build an in-memory storage engine, Casper, and we show that it outperforms state-of-the-art data layouts of analytical systems for hybrid workloads. Casper delivers up to 2.32x higher throughput for update-intensive workloads and up to 2.14x higher throughput for hybrid workloads. We further show how to make data layout decisions robust to workload variation by carefully selecting the input of the optimization.

Incremental lithography mask layout design and verification

Abstract: A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.

Computer-Aided Preliminary Layout Design of Customized MOS Arrays

Abstract: One of the most perplexing problems confronting device designers utilizing MOS technology is the development of an effective layout design methodology. This paper describes a versatile layout design scheme for customized digital-type MOS arrays utilizing four-phase clocking schemes (ratioless logic). The analytical characterization of this layout design scheme is defined through the introduction of p-order and m-order indices. The p-order indices are assigned to members of the Boolean equation set that define the relative placement of their mechanization areas (p-diffusion structures) on the MOS array. The m-order indices are assigned to members of the term set that define their relative placements within parallel metalization channels on the MOS array. The underlying variables influencing the algorithmic derivation of quasi-optimal p-order and m-order assignments are also discussed.