Parasitic capacitance

About: Parasitic capacitance is a(n) research topic. Over the lifetime, 10029 publication(s) have been published within this topic receiving 110331 citation(s).

On-chip spiral inductors with patterned ground shields for Si-based RF ICs

Abstract: This paper presents a patterned ground shield inserted between an on-chip spiral inductor and silicon substrate. The patterned ground shield can be realized in standard silicon technologies without additional processing steps. The impacts of shield resistance and pattern on inductance, parasitic resistances and capacitances, and quality factor are studied extensively. Experimental results show that a polysilicon patterned ground shield achieves the most improvement. At 1-2 GHz, the addition of the shield increases the inductor quality factor up to 33% and reduces the substrate coupling between two adjacent inductors by as much as 25 dB. We also demonstrate that the quality factor of a 2-GHz LC tank can be nearly doubled with a shielded inductor.

Physical modeling of spiral inductors on silicon

Abstract: This paper presents a physical model for planar spiral inductors on silicon, which accounts for eddy current effect in the conductor, crossover capacitance between the spiral and center-tap, capacitance between the spiral and substrate, substrate ohmic loss, and substrate capacitance. The model has been confirmed with measured results of inductors having a wide range of layout and process parameters. This scalable inductor model enables the prediction and optimization of inductor performance.

Power semiconductor devices and methods of manufacture

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Transformerless Inverter for Single-Phase Photovoltaic Systems

Abstract: When no transformer is used in a grid-connected photovoltaic (PV) system, a galvanic connection between the grid and the PV array exists. In these conditions, dangerous leakage currents (common-mode currents) can appear through the stray capacitance between the PV array and the ground. In order to avoid these leakage currents, different inverter topologies that generate no varying common-mode voltages, such as the half-bridge and the bipolar pulsewidth modulation (PWM) full-bridge topologies, have been proposed. The need of a high-input voltage represents an important drawback of the half-bridge. The bipolar PWM full bridge requires a lower input voltage but exhibits a low efficiency. This letter proposes a new high-efficiency topology that generates no varying common-mode voltage and requires the same low-input voltage as the bipolar PWM full bridge. The proposed topology has been verified in a 5-kW prototype with satisfactory results

Transformerless Single-Phase Multilevel-Based Photovoltaic Inverter

Abstract: The elimination of the output transformer from grid- connected photovoltaic (PV) systems not only reduces the cost, size, and weight of the conversion stage but also increases the system overall efficiency. However, if the transformer is removed, the galvanic isolation between the PV generator and the grid is lost. This may cause safety hazards in the event of ground faults. In addition, the circulation of leakage currents (common-mode currents) through the stray capacitance between the PV array and the ground would be enabled. Furthermore, when no transformer is used, the inverter could inject direct current (dc) to the grid, causing the saturation of the transformers along the distribution network. While safety requirements in transformerless systems can be met by means of external elements, leakage currents and the injection of dc into the grid must be guaranteed topologically or by the inverter's control system. This paper proposes a new high-efficiency topology for transformerless systems, which does not generate common-mode currents and topologically guarantees that no dc is injected into the grid. The proposed topology has been verified in a 5-kW prototype with satisfactory results.