Showing papers on "Parasitic capacitance published in 1968"

Circuit for reducing stray capacity effects in transformer windings

Abstract: A transformer charging system that provides a highly efficient operation and that substantially eliminates switching transients. The high voltage or secondary winding of the transformer as well as the primary winding in some arrangements, is divided into segments which are isolated from each other by unidirectional current conductive devices such as diodes. For charging a load coupled to the secondary winding, current pulses are repetitively applied to the primary winding from the power source with the flyback voltage resulting from the pulse terminations causing current to flow through the diodes. The diodes allow the stray capacitance associated with each segment to initially charge but prevent them from discharging between the repetitive operations, which would cause additional flow of primary current and dissipation losses.

Wafer-chip assembly for large-scale integration

Abstract: A technique has been developed for achieving a very high density interconnection of active silicon devices to permit the fabrication of large electronic subsystems in essentially monolithic form. The technique has been used to assemble a MOS 2000-bit shift register containing 12 000 MOS transistors on a 300 by 600 mils silicon substrate. The register utilizes ten 200-bit shift-register chips, each containing 1200 transistors. Four-phase MOS logic techniques are used to obtain very low power (0.1 mW/bit) and/or high frequency (10 MHZ) operation. In the technique used to assemble the 2000-bit shift register, silicon large-scale array chips are face-down bonded in adjoining positions on a larger silicon wafer section which may contain additional layers of interconnections and/or active devices as required to form a complete system subassembly. Since the same photoengraving technology is used in the substrate as on the chips, very high packing densities can be achieved, with minimum chip area required for interconnections. This approach also minimizes the parasitic capacitance associated with more conventional techniques for encapsulating and interconnecting large-scale arrays. In the case of MOS circuits, large area-buffer devices are not needed due to the small capacitance in the wafer-chip interconnections. Various techniques have been evolved for processing the chips and substrates produce contact regions which permit the required high fabrication yields. The bonding conditions and metallurgical systems used to date in fabricating large shift-register assemblies will be described and compared with other approaches.

Crossover for large scale arrays

Abstract: The subject invention relates to a method for providing crossovers in microelectronic circuitry. More particularly, the subject invention contemplates the fabrication of crossovers by deposition of insulative material on a conductor at the point of crossover and subsequent deposition of a crossing conductor over the insulative ''''bridge.'''' Additional advantages other than the elimination of point-to-point wiring methods include improved circuit reliability; room temperature circuit assembly; decreased manufacturing time; increased unit density; ''''flip-chip'''' utilization; and reduction of stray capacitance.

Method for making ambient atmosphere isolated semiconductor devices

Abstract: Disclosed are methods for making integrated circuits which use the ambient fabrication atmosphere as an isolation medium between elements of the circuit, such methods advantageously produce devices having improved mechanical structure, improved surface area for attaching lead wires, reduced collector area, and lower stray capacitance.

Active capacitance reactance circuit

Abstract: A VARIABLE IMPEDANCE CIRCUIT INCLUDING A CONSTANT CURRENT GENERATOR CONNECTED IN SERIES WITH AN ACTIVE CIRCUIT ELEMENT HAVING FEEDBACK PROVIDED BY A REACTIVE ELEMENT, AND MEANS TO VARY THE GAIN OF THE ACTIVE ELEMENT.

An Automatic Computer-Controlled System for the Measurement of Cable Capacitance

Abstract: A description is given of the application of automation to a classical measurement problem-determining the capacitance parameters of multiconductor communication cables. These parameters are important in the manufacture of cables and determine such factors as transmission efficiency, crosstalk, and noise. Although the desirability of automating these measurements has long been recognized, the problem of controlling stray capacitance in the switching equipment and connecting leads has previously prevented such automation. This problem has now been overcome by the use of a three-terminal guarded automatic bridge to measure the individual direct capacitances between conductors and a digital computer to calculate the desired parameters from these measurements. The benefits that have been realized by the inclusion of the computer in the measurement system are emphasized-increased speed, elimination of errors, flexibility of operation, data reduction and presentation, and self-testing.

Tuning circuit for multi-band receiver using variable capacitance diodes

Abstract: A RECEIVER ADAPTED TO RECEIVE SIGNALS WITHIN TWO FREQUENCY BANDS COMPRISES SEPARATE TUNING MEANS, EACH MEANS BEING ADAPTED TO RESONATE AT FREQUENCIES WITHIN ONE OF THE FREQUENCY BANDS. THE TUNING MEANS ARE EACH PROVIDED WITH SIGNAL SENSITIVE CAPACITANCES HAVING THE CHARACTERISTIC OF BEING OPERATIVE OR INOPERATIVE AS A CAPACITOR DEPENDING UPON THE POLARITY OF A CONTROL SIGNAL APPLIED THERETO. THE POLARITY OF THE APPLIED CONTROL SIGNAL THEREBY DETERMINES WHICH OF THE TUNING MEANS WILL BE OPERATIVE THEREBY RENDERING THE RECEIVER EFFECTIVE TO RECEIVE ONLY SIGNALS WITHIN THE SELECTED FREQUENCY BAND. WHEN A GIVEN CAPACITANCE IS OPERATIVE AS A CAPACITOR, THE VALUE OF ITS CAPACITANCE MAY VARY DEPENDING UPON THE MAGNITUDE OF THE CONTROL SIGNAL APPLIED THERETO. HENCE CONTROL SIGNAL APPLYING MEANS CAN SELECT A DESIRED BAND AND CAN EFFECT TUNING WITHIN THAT BAND.

Optionally clocked transistor circuits

Abstract: Inverting switching and logic function circuits for digital equipment are provided in networks with an option for phase clocking by including first and second insulated-gate (MOS), field-effect transistors having their source connected to the functional circuit output terminal. The drain and gate of the first transistor are adapted to be connected to a clock source for clocked mode of operation and to circuit ground for nonclocked mode of operation. The gate of the first transistor is also so connected to the functional circuit as to provide circuit ground thereto permanently for a nonclocked mode of operation, and to provide clock pulses thereto for a clocked mode of operation, such that the functional circuit is biased off in reference to circuit ground potential during clock pulses to charge stray capacitance at the functional circuit output terminal, but enabled as a function of one or more input signals between clock pulses to discharge the stray capacitance. The second transistor connected to the output terminal is adapted to be biased for conduction as a load transistor when the first transistor is connected to circuit ground such that the stray capacitance is then charged through the load transistor and discharged through the circuit as a function of one or more input signals in a nonclocked mode of operation for the network.

Instrument for measuring conductance or capacitance of an electrical load during operation

Abstract: Instrumentation for measuring electrical characteristics of a load during application of stored electrical energy to the load. The current to the load is accurately monitored over a wide dynamic range. An instrument including a current source for charging a capacitance, a switch for discharging the capacitance through a diode into the load, and an RC circuit for developing an output signal which is the derivative of the voltage across the diode, with this output signal being directly proportional to the conductance of the load at any time during the discharge of the capacitance. A similar instrument for measurement of capacitance of a load. The instruments are suitable for the measurement of conductance and capacitance of an electric emulsion treater during operation of the treater.

Resistance measuring bridge circuit including output gating means

Abstract: In a conductivity bridge a switching system is employed to allow only selected portions of the bridge output signal to pass through the output indicator meter. More specifically, initial portion of the signal waveform output, corresponding to the time during which the stray capacitance in the circuit is becoming fully charged, is prevented from passing through the meter, thereby eliminating the effect of such capacitance in the circuit and thus yielding a more accurate measurement of an unknown resistance.

Passive elements for solid-state integrated circuits

Abstract: A capacitor is formed for a monolithic integrated circuit with an increased capacitance without a decrease in breakdown voltage by forming the junction in a plurality of curved portions rather than a straight portion. The junction may be formed by either a single or double diffusion through parallel slots in a mask to permit diffusion. It also may be formed by either a single or double diffusion through orthogonal families of parallel slots. A resistor is formed by two diffusions to form the junction rather than a single diffusion whereby the gradient of the doping profile in the depletion layer of the junction is reduced. This reduces the parasitic capacitance at the junction for a given resistance whereby the resistor may be utilized at a higher cutoff frequency to permit the resistor to be utilized in higher frequency circuits.

Diffusion capacitance of p–n junctions and transistors

Abstract: The error associated with the quasi-steady-state (q.s.s.) calculation of the diffusion capacitance of an ideal semiconductor diode, already pointed out in the literature, is interpreted in terms of a transmission-line representation of the device. The analysis is extended for short-base diodes and transistors. It is pointed out that, for diodes and transistors, the q.s.s. approach introduces a systematic error by neglecting the distributed nature of these devices.

Determination of the constants of the capacitance/voltage law of a varactor diode

Abstract: A graphical method is proposed for finding the constants, including the stray capacitance, of the capacitance/voltage relationship of a varactor diode.

A solution of the selectivity problem

Abstract: A simple frequency-selective circuit is proposed having an arbitarily high Q and at the same time a minimal sensitivity. Use is made of an LC circuit and a special type of negative conductor.

Fast-sweep capacitance-voltage plotter

Abstract: A circuit for automatically plotting two-terminal capacitance versus voltage is described. In contrast to those previously announced, this circuit has the capability of permitting the use of a voltage sweep rate up to 0.1 times the carrier frequency. A fast sweep rate is useful in surface-state measurements on metal-insulator-semiconductor diodes and some results of this type of measurement are indicated for Si.

Current Comparator Using Ferromagnetic Cores and Its Application to Analog-to-Digital Converters

Abstract: A current comparator using ferromagnetic cores with a rectangular hysteresis loop is described. Design criteria for this comparator are derived from the B-H characteristics of the core. To verify the performance of the current comparator, basic experiments and experimental A-D converters with these comparators have been made. By application of the current comparator, it would be possible to realize an A-D converter that could convert a current between a few milliamperes and a few amperes into 9- to 10-bit binary forms within an order of microseconds. The merits of an A-D converter of this type are 1) its very low input impedance, 2) its high impedance between the balanced input terminal pair and the ground, and 3) its ease of conversion of the sum/difference of two currents. Because of these features, the A-D converters can measure currents in circuits having high potential to ground without giving disturbance. The input impedance, measured at 500 kHz, of the experimental A-D converter is shown as a series connection of 0.3-ohm resistance and 0.24-?H inductance, with a stray capacitance of 7.5 pF between input terminals and ground.

Calculation of the net and parasitic capacitances of diffused junctions

Abstract: Junction capacitance measured at two reverse voltages is sufficient to calculate the parasitic and the net junction capacitances of a transistor or diode Use of a nomograph further simplifies the calculation