Showing papers on "Parasitic capacitance published in 1972"

Storage array and sense/refresh circuit for single-transistor memory cells

Abstract: For the cell layout in silicon-gate technology a storage capacitor is proposed that uses a field-induced nonequilibrium inversion layer as an electrode. As a sensitive refresh amplifier a gated flip-flop that can be used for one digit line at each of its two input nodes is presented. Different cells and refresh circuits have been realized in silicon-gate technologies. Cells with an area of 1600 /spl mu/m/SUP 2/(2.6 mil/SUP 2/) have been successfully operated with a READ/WRITE cycle time of 350 ns (storage capacitance 0.134 pF, digit line capacitance 0.32 pF for 64 cells per line or 128 cells per amplifier).

Drain Feedback - A Novel Feedback Technique for Low-Noise Cryogenic Preamplifiers

Abstract: This paper describes a novel technique of charge restoration - the drain feedback, based on the characteristics of the gate-to-drain junction of the input FET. The restoration charge required at the input of the preamplifier is generated by impact ionization in high-field regions of the FET. Actually the feedback is obtained by regulating the drain voltage according to the input energy count-rate product and consequently adjusting the electric field for the necessary charge generation. In the first part of the paper the principles of impact ionization in semiconductors at cryogenic temperatures are outlined and applied to junction FET's (JFET's) under saturation conditions. Then, the properties of FET gate leakage current generated by impact ionization are analyzed. Finally, the continuous mode of operation of the new feedback method is presented, and results from its application in x-ray spectroscopy with silicon and germanium detectors are given. Superior noise and count-rate performance coupled with simplicity and reliability are the outstanding features of the drain feedback method. It is the first feedback method in which the cryogenic input stage comprises the detector and the FET without the parasitic increases of stray capacitance or light-induced leakage currents characteristic of the other resistorless configurations.

Eliminating threshold losses in MOS circuits by bootstrapping using varactor coupling

Abstract: Threshold losses reduce speed and increase power consumption of MOS digital circuits. A method to eliminate these losses is described. This is accomplished by the application of bootstrapping, in which a temporarily isolated circuit node is capacitatively coupled to the input voltage. The advantages of a MOS varactor element and its use for the coupling capacitor are described.

Method and apparatus for direct measurement of percent

Abstract: In one preferred embodiment, a percentage water measuring circuit is shown by providing a capacitance probe for measuring the capacitance of an oil-water emulsion, a reference capacitor of known value in series with capacitance probe, a variable gain a-c voltage generator connected in series with the reference capacitor and the capacitance probe for applying an a-c voltage across each, a voltage measuring circuit for measuring the actual voltage differential across the capacitance probe, an error detecting circuit for detecting the difference between the actual voltage differential across the capacitance probe and a predetermined voltage, the error detecting circuit controlling by a feedback path the variable gain generator to maintain the voltage differential across the capacitance probe at the predetermined level, a voltage measuring circuit for obtaining the voltage differential appearing across the reference capacitor, the voltage differential being directly related to the percentage water appearing in the oil-water emulsion, and a nonlinear to linear function generator to convert the voltage differential to a linear function with respect to percentage water

Electrical analysis of interconnections in a solid state circuit environment

Abstract: A new technique for analyzing the transmission properties of dense integrated circuit interconnections will be discussed. Analytical methods for calculation of appropriate equivalent circuit elements representing conductor geometries will be presented.

A Principle for Capacitance Measurement, Suitable for Linear Evaluation of Capacitance Transducers

Abstract: A principle for measurement of capacitance is shown, together with a practical realization. The inherent linearity of output voltage as function of capacitance makes the principle advantageous for the evaluation of capacitance transducers.

Marx surge pulser having stray capacitance which is high for input stages and low for output stages

Abstract: A high voltage pulse generator of the Marx surge type is described in which the stray shunt capacitance to ground associated with the first several spark gaps of the input stages is of a higher value than the stray capacitance associated with the spark gaps of the output stages. The high stray capacitance of the input stages increases the amount of over-voltage transmitted to succeeding gaps when earlier gaps break down which enables a wider pressure range between the self fire and no fire pressures of the gas in the spark gaps. However, by providing a low stray capacitance for the output stages the pulser is still capable of producing high voltage output pulses of a narrow width and fast rise time. These different stray capacitances are provided by placing a grounded metal sleeve of smaller diameter than the pulser housing around the first few storage modules forming the input stages of the pulser, while leaving the last few storage modules forming its output stages free of any such sleeve. As a result, the storage modules of such output stages are spaced from the grounded metal housing by a greater distance than the spacing between the input modules and such sleeve to provide a lower stray capacitance for the output modules than for the input modules.

Analysis of limit cycles in a two-transistor saturable-core parallel inverter

Abstract: One of the earliest-developed and still widely-used dc to square-wave inverters is the Royeror Uchrin-Taylor configuration shown in Fig. 1. Although the circuit is composed of very few components, its proper operation depends on complex interactions of the transformer as it switches between its unsaturated and saturated regions, and the tow transistors as they switch between cut-off and saturation. Numerous qualitative descriptions of the operation of this circuit have been presented; however, the complexities introduced by the multiple nonlinearities are such that few mathematically based analyses have been presented, and these have been rather limited in scope (1,2,3,4). The analysis presented in this paper provides insight not only into steady-state operation but also into the transient behavior of the circuit. It also makes evident the influence of certain small, often neglected, parasitic elements such as winding capacitance, transformer saturation inductance, and semiconductor junction capacitances.

Large-value monolithic resistors for micropower integrated circuits

Abstract: The minimum power dissipation of micropower integrated circuits is often limited by the availability of large-value monolithic resistors. Two major types of field-effect resistor structures are examined and an analysis of the primary factors that determine sheet resistance and parasitic capacitance is presented. Resistor tolerance, linearity, and temperature coefficient are briefly discussed. It is shown that resistors with sheet resistances greater than 50 k/spl Omega///spl square/ and parasitic capacitances less than 0.002 pF/k/spl Omega/ can be readily fabricated in a monolithic structure.

New solid-state image scanner capable of random positioning

Abstract: Studies were carried out on a solid-state image scanner that is able to scan and be addressed randomly. It consisted of a linear integrated-circuit array of photodiodes and metal-oxide-semiconductor transistors (MOST). It was found that the maximum scanning rate is about 1.5/spl times/10/SUP 5/ dot/s and that the value is mainly restricted by the charge-storage effect in the photodiode and stray capacitance between the gate and the source electrode of the MOST.