Showing papers on "Parasitic capacitance published in 1977"

Evaluation of the size of a plant's root system using its electrical capacitance

Abstract: This paper extends an earlier one5. The relationship between electrical capacitance of a plant root system (C) and size (weight, volume, surface) of the root system (x) can be expressed by equation of the line $$C = a + bx$$ ifa equals size of parasitic capacitance of measurement, i.e. capacitance of soil, wires,etc. andb equals regression coefficient influenced by type of soil plant species, measuring frequency and voltage,etc.

Equivalent Circuit Capacitance of Microstrip Step Change in Width

Abstract: Calculated results which extend existing data on the capacitance of step discontinuity are presented for w/sub 1/ /H of value 0.1, 0.5,1.0, and 2.0, for relative dielectric constants of 15.1, 9.0, 4.0, and 2.3, and for w/sub 2/ /H in the range 0.1-10.0. The quasi-static method of calculation is used, and the excess capacitance associated with the steps is determined by the solution of the integral equation using Green's functions.

Capacitive touch-pad devices with dynamic bias

Abstract: A dynamic biasing capacitance is formed between a transmitting electrode and a receiving electrode of a capacitive touch-pad device to couple a portion of the scan voltage signal into the sense node of a voltage comparator circuit, coupled to the receiving electrode, to offset the comparator circuit threshold voltage. The dynamic biasing capacitance may be formed by overlapping portions of the electrodes, with a dielectric layer positioned therebetween, or by the parasitic capacitance between aligned end surfaces of the two electrodes, with the magnitude of the dynamic biasing capacitance being adjusted by variation of interelectrode geometries.

Package for push-pull semiconductor devices

Abstract: A semiconductor package for containing two individual devices such that they may be externally connected in a push-pull relationship. Two transistors, each having an input and output pad are formed on the same dielectric wafer, in a spaced relationship with each other and a ground plane so as to form two separate transmission line paths. The transistors are wired either in a grounded emitter or grounded base configuration. A shunt inductor is formed by a metallized strip or lead bond from the collector of one transistor to the collector of the other transistor. This inductor reduces the influence of the parasitic capacitance in the equivalent output circuit of the transistors. Since the collectors of both transistors are at the same DC level it is not necessary to include a DC blocking capacitor in series with the inductor. This increases the reliability and the reproducibility of the circuit because bonding wires necessary in prior devices to connect the blocking capacitor in series with the output inductance is not necessary. This packaging technique increases the output impedance, decreases the internal losses, and increases the bandwidth when wired as a push-pull circuit.

Low parasitic capacitance and resistance beamlead semiconductor component and method of manufacture

Abstract: A beamlead semiconductor component and a method for manufacturing the semiconductor device with low parasitic capacitance and electrical resistance is provided. The beamlead component includes a thick layer of glass forming one end of the component directly beneath one of the beamleads and extending up to the edge of the active device on the beamlead surface of the component. On the opposite side of the active device from the glass layer is a metalized cavity that provides the electrical contact for a second beamlead with the semiconductor substrate. From the other surface, the non-beamlead surface, of the component another metalized cavity adjacent to the active region of the component and the metalized cavity on the beamlead surface has been etched. The cavity in the other surface of the component exposes a portion of the deepest surface of the metalization in the cavity on the beamlead surface to make electrical contact between the two metalizations. These interconnected cavities thus provide an electrical via between the two surfaces of the component. The use of the thick layer of glass beneath the one beamlead provides a considerable reduction in the parasitic capacitance between this beamlead and various layers of the substrate to which it is not connected. The metalized cavity in the other surface of the component substrate and the via reduces the resistance of the device by thinning the substrate beneath the active region and limiting the length of longest current path through the semiconductor material to a single thickness of that material.

System and method for determining capacitance and cable length in the presence of other circuit elements

Abstract: Method and apparatus utilizing constant current charging and discharging to determine the capacitance of a telephone cable or other circuit element. An output signal corresponding to the time required to increase the voltage from a first level to a second level and back to the first level corresponds to the capacitance of the element and, in the case of a cable, the length of the cable.

Microelectrode amplifier with improved method of input-capacitance neutralisation.

Abstract: A circuit is described which allows the input capacitance of an f.e.t. input integrated circuit to be used both as the feedback capacitance to neutralise the total input capacitance and to inject current pulses into the input. Compared with the conventional method of adding discrete capacitors to perform these functions, this design results in a lower total capacitance at the input, which reduces the high-frequency noise generated by the amplifier and facilitates the achievement of a low effective capacitance. A modified version having an ultralow (0·1pA) input current, for use with ion-sensitive microelectrodes, is also described.

Selective diffusion and etching method for isolation of integrated logic circuit

Abstract: An integrated injection logic circuit, wherein the inverted, multi-collector transistor of each cell includes active base regions separated by dielectric isolation, and wherein a heavily-doped channel-stop layer is selectively located along the sidewalls of the isolation, to prevent collector-to-emitter surface inversion leakage. The isolated geometry substantially reduces parasitic capacitance between the substrate and the extrinsic base, thereby increasing the switching speed of the device.

Ratioless type MIS logic circuit

Abstract: A ratioless type MIS logic circuit comprises a logic block including at least one depletion mode FET inherently having a gate-to-source parasitic capacitance and a gate-to-drain parasitic capacitance, an output capacitance, a circuit for precharging the output capacitance and depletion mode clamping FETs connected one with each of the two ends of the logic block, the clamping FETs having their gates connected with a reference potential and the threshold voltage value of the FET in the logic block being larger than those of the clamping FETs.

Frequency linearization and sensitivity equalization of a frequency modulated crystal oscillator

Abstract: A direct FM modulator includes an oscillator comprising a current conducting device providing amplification to sustain oscillations and a frequency determining circuit connected thereto for controlling the frequency of oscillation. The frequency determining circuit includes a piezoelectric element in series with a voltage variable capacitance and an adjustable capacitance coupled across this series combination. The capacitance of the voltage variable capacitance is changed by a modulating voltage to provide frequency deviation about the center frequency of oscillation. A frequency linearization of the crystal oscillator is provided by a selected value of capacitance coupled across the varactor and the capacitance value of the adjustable capacitance such that the frequency deviation vs. voltage is maximum at the initial reference bias voltage and is symmetrical about this reference bias.

Voltage variable integrated circuit capacitor and bootstrap driver circuit

Abstract: An integrated circuit junction capacitor is formed using conventional bipolar transistor technology. Voltage variable capacitance is provided by a reverse biased emitter-base junction and parasitic collector-base capacitance is isolated from the emitter-base capacitance by maintaining the base-collector junction in a reverse biased condition. A bootstrapped driver circuit is also described in which bootstrap current is provided by a transistor-like structure in which an internal load capacitance enables circuit performance to remain substantially constant under various driven load conditions.

Beam lead dual parametric amplifier

Abstract: A parametric amplifier having a beam lead dual Schottky barrier diode fabricated on a single semiconductor chip across a waveguide cavity. Two anode leads are bonded to the adjacent waveguide walls for coupling to a pump source; and a common cathode lead is bonded to a signal circuit. Parasitic reactances are reduced by minimizing stray capacitance and beam lead series inductance.

Electric knife and electric operating method

Abstract: An improved electrosurgical safety circuit where the currents in the active and patient leads are monitored, the monitored currents being respectively rectified and then subtracted from one another. Whenever the active current exceeds the patient or return current by an amount corresponding to a dynamically variable threshold, an appropriate measure is taken such as the sounding of an alarm and/or the de-energization of the electrosurgical generator. The dynamic threshold varies in accordance with the level of the signal applied to the patient and compensates for leakage current through stray capacitance from the active lead to ground.

Surface wave filter

Abstract: PURPOSE:To reduce the affect due to capacitance between electrodes or stray capacitance by providing the conductor layer on the insulating layer covering the comb type input and output electrodes, and to improve and keep a long time for the performance

Isolation amplifier having improved fidelity

Abstract: An isolation amplifier comprising three separate conductively-isolated sections: (1) an input section including an AC modulator, (2) an output section including a demodulator, and (3) an improved oscillator or AC power section for reducing the undesirable effects of common mode interference signal sources coupled thereto through stray capacitance. The improved oscillator or power portion includes control elements for controlling the timing and direction of current conduction through the primary winding of a transformer having its secondary connected to the chopper or modulator. The control elements and circuitry associated therewith conduct in alternation and in a manner resulting substantially in conduction-overlap. Such conduction overlap is accomplished by means which accelerate initiation of conduction in one control element and possibly also retard the cessation of conduction in the other control element. In one embodiment, the conduction controlling circuitry of the AC power section includes two pairs of oppositely-conductive types of semi-conductors having their collector-emitter circuits connected in series with the transformer primary and across a DC power buss. Conduction-control of the respective semi-conductors is effected by a square wave control signal applied to the respective base elements thereof through respective speed-up capacitors.

Variable frequency oscillator

Abstract: PURPOSE:To make it possible to vary oscillated frequencies without using any unstable elements, in spite of that, to receive no influence from stray capacitance in inductance elements, noise in amplifier unit, and so forth.

FET device with reduced gate overlap capacitance of source/drain and method of manufacture

Abstract: A metal gate transistor is fabricated to have reduced gate overlap of source/drain regions and increased oxide thickness over the diffused regions whereby parasitic capacitance is reduced and switching speed is increased. The method comprises the steps of (1) selecting an appropriate insulating thickness over a semiconductor substrate, (2) forming source/drain diffused regions in the substrate through openings in the insulating layer at appropriate diffusion temperatures, (3) selecting an appropriate drivein and regrowth temperature whereby the insulating layer thickness over the diffused region is greater than that over the non-diffused region and out diffusion of the diffused regions is minimized, (4) etching the region between the source/drain to form a gate area and (5) growing a prescribed gate insulation thickness for a metal gate whereby the gate insulation overlap of the diffused region and the thickness of the gate insulation overlap of the diffused region reduce the parasitic capacitance and increase the switching speed of the resulting metal gate transistor relative to prior art transistors.

Schottky diode mfr. with low stray capacitance - by proton bombarding region surrounding diode

Abstract: Schottky diodes having a metallic deposit in contact with a first semiconductor region are bombarded with protons in a second semiconductor region surrounding the first to diminish the parasitic capacitances set up between the surrounding surface and the lead wires attaching the diodes to their associated working circuits Used at frequencies >=309 Hz, in the min wave band, the stray capacitances which lead to high losses are considerably reduced Leads may be attached to the front of the diode rather than the reverse, leading to simpler circuit designs Beam lead devices can be made

Very high frequency tuner for eliminating image interference and stray capacitance effects

Abstract: A very high frequency tuner for selection of a broadcasting signal through mechanical switching selection of inductance coils, comprising a radio frequency amplifying transistor of an automatic gain control type connected to amplify a high frequency signal, a single tuned coupling circuit coupled to said high frequency amplifying transistor for selectively withdrawing a tuned high frequency signal, a local oscillator for providing a local oscillation frequency signal the frequency of which is different by a given frequency difference from the said selectively withdrawn tuned high frequency signal, a mixer responsive to the tuned high frequency signal from the tuned coupling circuit and the local oscillation frequency signal for providing an intermediate frequency signal, an automatic gain control signal source for applying the automatic gain control signal to the high frequency amplifying transistor, said transistor having a stray capacitance at the output thereof, said single tuned coupling circuit comprising a πtype single tuned coupling circuit comprising mechanically selected coil arranged in a series fashion between the output of the high frequency amplifying transistor and the input of the mixer, an input capacitor connected to the input terminal of the selected inductance coil in a shunt manner and a second capacitor connected to the output terminal of the inductance coil in a shunt manner, wherebysaid stray capacitance being shunted by said input capacitor.

Determination of dopant profiles by voltage measurements

Abstract: The dopant profile in the channel of a double-gated J-FET with uniformly doped channel and substrate is determined from measurements of gate voltage pairs at pinchoff. This procedure offers advantages over the C-V method in cases of imprecisely known gate area, or in the presence of significant stray capacitance.

Semiconductor for high frequency

Abstract: PURPOSE:Highly reliable and easily usable high frequency semiconductor device is obtained having high output power without damage at the position where the stray capacitance is generated.

Electronic circuit for floating Langmuir double probe used in pulsed plasma diagnostics

Abstract: An electronic circuit used with floating Langmuir double probes in pulsed plasma measurements is described. Current fluctuations of the double probe are transformed by means of a special transformer into voltage fluctuations. The signal is then integrated to give a voltage wave proportional to the measured current wave. A bridge circuit has been used to neutralize the influence of current‐source stray capacitance.

A Charge-oriented Model For MOS Transistor Capacitances

Abstract: A new model for computer simulation of capacitance effects in MOS transistors is presented. Transient currents are found directly from the charge distribu- tion in the device rather than from capacitances. The effective capacitances which result are non-reciprocal. The model guarantees conservation of charge and includes bulk capacitances. Several circuit examples are considered.

Low-frequency stability of impatt-diode circuits

Abstract: The maximum available stability of an impatt-diode circuit depends on the parasitic capacitance measured at the diode terminals. A formula is given relating the microwave characteristics of the circuit to the maximum parasitic capacitance compatible with freedom from spurious oscillation.

Analysis of forward-bias p-i-n-diode inductive driving

Abstract: Published literature on p-i-n-diode driving circuits for phase-shifter applications is rather rare and contains descriptions or analyses of driving circuits with at least two high-power transistors as output devices. This paper presents design criteria for a high-power p-i-n-diode inductive driver, as well as analytical and experimental results for the forward-bias transition of p-i-n-diodes. Expressions are developed that enable one to predict the switching waveforms and the p-i-n-diode storage charge with very good accuracy. In developing these expressions the effects of circuit parameters and the parasitic capacitance due to the p-i-n-diode packaging and phase-shifter mounting have been taken into account.