Showing papers on "Parasitic capacitance published in 1978"

A charge-oriented model for MOS transistor capacitances

Abstract: A new model for computer simulation of capacitance effects in MOS transistors is presented. Transient currents are found directly from the charge distribution in the device rather than from capacitances. The effective capacitances which result are nonreciprocal. The model guarantees conservation of charge and includes bulk capacitances. Several circuit examples are considered.

Electromechanical transducer-coupled mechanical structure with negative capacitance compensation circuit

Abstract: Arrangements are disclosed for substantially reducing the effect of the inherent transducer capacitance in a transducer-coupled electromechanical system which is subject to vibrational movement. Electrical circuitry is coupled across the transducer output to provide a negative capacitance having a magnitude substantially the same as that of the inherent transducer capacitance, thereby substantially nullifying the inherent transducer capacitance and enabling improved damping (including low-noise damping) to be achieved.

Electronic circuit analysis and design

Abstract: Fundamentals of Electronic Circuit Analysis and DesignMicrowave Active Circuit Analysis and DesignElectronic Circuits (Sie) 3EIntroduction to Electrical Circuit AnalysisFoundations of Analog and Digital Electronic CircuitsFast Analytical Techniques for Electrical and Electronic CircuitsAnalog Circuit DesignElectronic CircuitsIntroduction to Linear Circuit Analysis and ModellingMicroelectronicsIntroduction to Circuit Analysis and DesignPower ElectronicsMicroelectronics Circuit Analysis and DesignElectronic Circuit Analysis and DesignComputer Methods for Circuit Analysis and DesignAnalysis and Design of Electronic Circuits Using PCsFundamentals of Electronics: Book 1Microelectronic Circuits: Analysis and DesignElectronic Circuit Analysis:Tolerance Design of Electronic CircuitsElectronics and Circuit Analysis Using MATLABIntuitive Analog Circuit DesignElectronic Circuit Analysis and DesignComputer Methods for Circuit Analysis and DesignElectronic Circuit Analysis and DesignCircuit AnalysisIntroduction to Electronic Circuit DesignAdvanced Electronic Circuit DesignElectronic Circuit Analysis and DesignMosfet Modeling for Circuit Analysis and DesignElectronic CircuitsCircuit Analysis For DummiesMicroelectronic CircuitsElectronic Circuit Analysis and DesignElectronic Circuit AnalysisElectronic Circuit Analysis and DesignElectronic Circuit DesignElectrical Circuit Analysis and DesignCircuitsElectronic Circuit Analysis and Design

Protective circuit on insulating substrate for protecting MOS integrated circuit

Abstract: A MOS integrated circuit comprises a MOS IC body including at least one MOS transistor made of an island-like semiconductor layer formed on an insulating substrate, and a protective circuit connected between a signal input terminal and the gate electrode of a MOS transistor at least at an input stage of the MOS IC body and adapted to protect the MOS integrated circuit against an irregular input signal. The protective circuit is also connected between ground and the gate electrode of the MOS transistor at the input stage of the MOS IC body and comprises a protective MOS transistor made of an island-like semiconductor layer formed on the insulating substrate in a manner to be arranged in juxtaposition with the MOS transistor at the input stage of the MOS IC body, a resistor connected between the signal input terminal and the gate circuit of the MOS transistor as the input stage of the MOS IC body the resistor being formed on a grounded insulating layer on the semiconductor layer overlying the insulating substrate to provide a stray capacitance therebetween, the resistor being formed in juxtapositon with the protective MOS transistor.

PSA-a new approach for bipolar LSI

Abstract: Describes a new fabrication method to realize bipolar LSI The new process, called the PSA (polysilicon self-aligned) method, is based on a new fabrication concept for dimensional reduction The process provides smaller PSA transistors with smaller parasitic capacitance by being combined with local oxidation technology As a production example of this modified PSA method, a static bipolar 4K TTL RAM has been manufactured In this production, the nonepitaxial technology (triple diffusion) has also been adopted to shorten production turnaround time and to increase fabrication yield Furthermore, PSA transistors have been combined with polysilicon diodes (PSD) and Schottky barrier diodes (SBD) to obtain low power Schottky diode-transistor logic (DTL) gates

Methods of and apparatus for controlling capacitance unbalance-to-ground in cables

Abstract: Capacitance unbalance-to-ground between conductors of a twisted pair, each of which may be insulated with at least a layer of cellular plastic insulation, is maintained within acceptable limits by controlling the extrusion of the insulation to maintain the measured coaxial capacitance and associated outside diameter of the insulated conductors within a range of values which correspond to acceptable capacitance unbalance-to-ground values.

Analysis of electrical equivalent circuit elements of piezo-tuning forks by the finite element method

Abstract: A finite element method (FEM) employing three-dimensional (3D) linear piezoelectric solid elements is used to analyze the vibrational characteristics of piezo-tuning forks. From this information, the equivalent circuit elements such as equivalent inductance, capacitance, mass and capacitance ratio can be calculated. Stable piezo-tuning forks can easily be adapted as mechanical filters by addition of couplers. Besides the aforementioned equivalent elements, it is necessary in filter design to ascertain the ideal transformer ratios which relate to the coupling between the tuning forks forming the filter. A method for estimating these ratios is presented. An example of a particular tuning fork using two candidate materials, quartz and lithium tantalate, is given to illustrate the finite element analysis and the calculations of the equivalent circuit elements.

Video signal play-back circuit

Abstract: In a video signal play-back circuit connected so that a play-back signal from a magnetic head may be applied to an amplifier circuit through a resonance circuit which consists of an inductance element and a capacitance element, a resistor for adjusting the quality factor Q of the resonance circuit is connected between one terminal of the resonance circuit and one output terminal of the amplifier circuit, thereby to reduce thermal noises which develop from the Q adjusting resistor.

Battery-operated body capacitance intrusion alarm apparatus

Abstract: An intrusion alarm having an oscillator which is turned off by the body capacitance of a would-be intruder operates in the frequency range of 17-65 MHz. At this frequency, reliable discrimination between body capacitance and stray capacitance is possible and therefore sensitivity is increased while false alarms are reduced. Battery life is increased by providing a high resistance load in the stand-by mode to reduce battery drain to 500 microamperes or less. Latching and nonlatching embodiments are disclosed.

40-MHz CMOS-on-sapphire microprocessor

Abstract: Silicon-on-sapphire (SOS) technology has been applied to the RCA COSMAC microprocessor to obtain a high-speed single-chip CPU. The chip has 4827 transistors and measures 5.3 mm square. The low device count is obtained through use of bit-serial arithmetic logic, a byte-serial incrementer, and a 5-transistor static storage cell. The low parasitic capacitance of the SOS structure permits a 40-MHz clock rate at 14 V.

Antenna tuning circuit

Abstract: An antenna tuning circuit of the type having a first variable capacitance diode connected in parallel with a coil to form a resonance circuit and a second variable capacitance diode through which the resonance circuit is connected to an antenna, in which the connection position of the first variable capacitance diode to the coil is adapted to be changed for the reduction in the image interference ratio. Reductions in the maximum capacitance and the ratio between the maximum capacitance and the minimum capacitance required for the variable capacitance diodes are also intended by the connection of a third variable capacitance diode to the antenna side of the second variable capacitance diode.

Semiconductor integrated amplifier

Abstract: A semiconductor integrated amplifier having a p-channel type MISFET and an n-channel type MISFET which are integrated in a single semiconductor substrate, a load resistance connected between the drain regions of the MISFETs, a power source to which the MISFETs are connected in series, and a DC current blocking capacitor through which the gates of the MISFETs are connected to each other. The amplifier has a gate capacitance one terminal of which is constituted by a well formed in the substrate and connected to high voltage side of power supply, while the other electrode thereof is constituted by a gate electrode formed on the well and connected to the low voltage side of the power supply. Parasitic capacitance of the capacitor is considerably reduced to allow a wider range of frequency adjustment of the amplifier.

4-µm LSI on SOS using coplanar-II process

Abstract: SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving the power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is 7 \times 10^{-11} A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (V TD ) to be -2.1 V. This is attributed to the higher temperature dependence of V TD than that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.

Molybdenum gate MOS applied to an AM/FM digital frequency synthesizer

Abstract: An n-channel molybdenum self-aligned gate MOS technology has been developed and applied to an AM/FM digital frequency synthesizer. A high-frequency programmable divider operating at 180 MHz has been achieved by the use of molybdenum, low parasitic capacitance structures and zero-threshold MOS transistors, while maintaining conventional design rules. Molybdenum gate MOS has enabled the realization of a single-chip system, which consists of a directly programmable divider for the AM/FM local oscillators, a reference counter, a phase comparator, a circuit for dial tuning, and memories for storing the frequencies for 16 stations. A differential comparator has been fabricated on the LSI chip to simplify digital tuning in the receiver.

Insulating gate type field effect transistor and its manufacture

Abstract: PURPOSE:To manufacture IG FET having no punch through between the source and the drain and also having less parasitic capacitance between the substrate and the sourece or the drain

High speed bipolar CCD input structure

Abstract: A new and novel bipolar structure has been formulated for use with high speed charge coupled devices. The new CCD input structure addresses and overcomes the limitations inherent in conventional CCD input structures. Specifically the technique for metering analog charge packets into this CCD does not require multiple operations nor special clocking or gating pulses. Also, this bipolar input structure reduces significantly the effects of parasitic capacitance through the use of a bipolar mirror circuit geometry. Computer calculations predict that the operating bandwidth of this input structure should exceed one gigahertz bandwidth. Moreover, calculations show that the transfer linearity is significantly better than 1% as evident from ac and dc distortion analysis. The geometry of this bipolar input structure is process compatible with buried channel CCD.

Dual channel capacitance measurement device

Abstract: The capacitance of an unknown capacitor is determined by counting the cycles of a known frequency contained within a time gate whose time duration is determined by subtracting a gate whose length is equivalent to the stray measuring capacitance from a gate whose length is determined by the capacitance of the unknown capacitor plus the unavoidable stray measuring capacitances

Method for reducing parasitic capacitance in integrated circuit structures

Abstract: A method for reducing parasitic capacitance in semiconductor devices, particularly for the removal of raised portions of conductive layers overlying and capable of being capacitively coupled to other conductors in semiconductor memory integrated circuits. The method provides for the application of a masking or photoresist layer over the surface of a substrate containing portions of a conductor to be removed such that the masking layer completely covers the conductor. Next a uniform thickness of the masking layer is removed to expose only the raised portions of the conductor which are subsequently selectively etched through the remainder of the masking layer. Application of the method to a manufacturing process for a dynamic MOSFET memory array is also described in which bit sense line capacitance is substantially reduced.

A Subnanosecond Masterslice LSI Using Dielectric Isolation and Three Layer Metallization Technologies

Abstract: A high speed bipolar masterslice LSI has been realized which contains 400 internal gate cells and 60 output gate cells on a 5.7 mm × 5.7 mm chip. Oxide isolation with n-type epiataxial layer and three layer metallization by PMP structure are used for fabrication process. These new technologies afford a large reduction in device size, parasitic capacitance and wiring area, which improve LSI performance. An internal gate is realized by the CML circuit with a 400 mV logic swing and with emitter followers, together with extensive use of emitter-dotting and collector-dotting. Power supply voltage is -3.2 V and output level is compatible with standard ECL. The ALU chip has been fabricated for an application of this masterslice LSI and a 1.48 ns average propagation delay per circuit has been achieved.

Crystal oscillator with reduced power consumption

Abstract: A crystal-controlled oscillator having a switching transistor connected in series with the crystal tank circuit and amplifier of the oscillator.Power consumption is reduced by minimizing the tank circuit capacitance being charged and discharged by the amplifier. The tank circuit capacitance is reintroduced into or coupled to the amplifier circuit during a submultiple oscillation period to receive regenerative feedback from said amplifier circuit to thereby replenish the tank circuit energy losses.

Radio receiver aerial tuning circuit - has capacitance diode in resonant circuit whose min. voltage frequency coincides with mirror frequency (NL 23.10.78)

Abstract: The circuit has a first variable capacitance diode (C1) in parallel with a coil (L) and forming with it a resonant circuit, and a second capacitance diode (C2) connecting the coil (L) to the aerial (ANT). Its capacitance is controlled together with that of the first diode (C1). One coil (L) terminal, together with first capacitance diode (C1) terminal is earthed through a large capacitance capacitor (CE). The tuning voltage is collected from the capacitor two terminals. The resonant circuit parameters are such, that the frequency corresponding to the tuning voltage minimum coincides with a mirror frequency to be eliminated.

A new single-chip C/sup 2/MOS A/D converter for microprocessor systems-Penta-Phase Integrating C/sup 2/MOS A/D converter

Abstract: A new unique conversion technique named the `Penta-Phase Integration' method, applied to a single-chip C/SUP 2/MOS 12-bit analog-to-digital converter designed for microprocessor system, is introduced and described. The newly developed device, fabricated with a standard metal gate CMOS process including an 8-channel multiplexer and TTL compatibility, has several features: unipolar- and ratiometric-conversion can be performed; conversion accuracy within /spl plusmn/0.05 percent of full scale over the -35/spl deg/C-+85/spl deg/C temperature range can be obtained; conversion time is 1.1 ms at a 20 MHz clock frequency, and the device can be operated with a single 5 V power supply and 6 mW power consumption at a 4 MHz clock frequency. The new technique essentially incorporated several methods which divide one conversion cycle into five-phases, accomplish minimization of the error caused by comparator response delay, provide several narrow flat phases to eliminate switching errors due to parasitic capacitance, and enable high clock frequency operation in digital circuits by utilizing C/SUP 2/MOS circuit technology and a synchronized configuration for counters.

J-band performance of 300 nm gate length GaAs FETs

Abstract: Present noise theories

Electronic comparative capacitance measurement device - produces integrated pulse width modulated capacitance proportional signals using monostable circuits (NL 7.8.78)

Abstract: An electronic capacitance measurement device, esp. for measurement of capacitances of the order of picofarads, converts capacitance variations into proportional current or voltage variations. A monostable multivibrator triggered by rectangular pulses is used for pulse shaping, and each capacitance to be measured is connected as part of the charging circuit of a monostable flip-flop whose pulse width corresp. to the capacitance. The device is used for comparative measurement of two variable capacitances varying with physical parameters such as temp., press., fluid volume etc. One capacitance varies with the parameter being measured, the other compensates unwanted effects. The flip-flops are triggered by an alternating voltage of extremely stable frequency. The pulse duration modulated output signals are integrated and fed to an indicator.

Electrostatic induction transistor logic element

Abstract: PURPOSE:To quicken the operating speed of element, while sufficiently giving the effect of reduction in parasitic capacitance through the use of low impurity concentration channel domain, by taking the gate domain for the sectional area spread in the bottom through the use of ion injection method.

Protective device for an electron tube

Abstract: A device comprising an electron tube having two electrodes between which a potential difference generated by a high voltage generator exits. A protection circuit is connected between these electrodes to protect the device against excess voltages. The protection circuit consists of a series network of a capacitor having a capacitance which is substantially higher than the parasitic capacitance beween the electrodes and a number of diodes whose forward direction extends from the electrode of highest potential to the electrode of lowest potential.

Iil semiconductor device and its manufacture

Abstract: PURPOSE:To manufacture I l constitution, by making the parasitic capacitance small thru low concentration of n type collector and by picking up the electrode without performing conventional n diffusion from the collector

Push-pull amplifier output circuit

Abstract: A high frequency push-pull amplifier which includes an improved output circuit to eliminate spurious emissions, typically low frequency parametric oscillations. The output circuit includes a low pass filter with an inductive input so as to avoid a series resonance to any harmonic of the desired output signal of the amplifier. A resistive termination is provided to any of the in phase signal components between the push-pull amplifier and the low pass filter. Also, to inhibit any tendency towards parametric oscillations, the variation in output capacitance with respect to collector voltage of the transistors is minimized by placing a capacitor in parallel with the collector capacitance, which is several times the collector to emitter capacitance of the transistors at their normal collector voltage.

Optically coupled isolators

Abstract: 1503065 Optical isolator NATIONAL SEMICONDUCTOR CORP 28 June 1976 [30 June 1975] 26808/76 Heading G1A In an optical isolator, comprising a light emitting diode 24 and a light-sensitive diode 26, the effects of stray capacitance between the diodes 24 and 26 is mitigated by subtracting the output of a "blind" light-sensitive diode 32 from the output of the light-sensitive diode 26. The further light-sensitive diode 32 which is shielded from light, is positioned so as to be subjected to substantially the same amount of stray capacitance as the diode 26. The subtraction is effected by a differential amplifier 33. Thus the differential amplifier's output signal is substantially free from the effect of stray capacitance. The further light-sensitive diode may be shielded from light by covering it with an opaque material such as black epoxy resin. In a modification Fig. 4 (not shown), the common mode rejection of the isolator may be enhanced by using diodes whose anodes are grounded.

Manufacture for mis type semiconductor device

Abstract: PURPOSE:To manufacture FET of high performance, by producing the source and the drain with the impurity domain having shallow and deep parts through ion injection once and by reducing the parasitic capacitance between the electrodes.