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Showing papers on "Parasitic capacitance published in 1979"


Journal ArticleDOI
TL;DR: A two-stage weighted capacitor network for A/D and D/A conversion utilizing a feedback amplifier and a discussion of the comparative accuracy and area of one- and two- stage weighted capacitor DAC's on the basis of capacitor tracking is given.
Abstract: A two-stage weighted capacitor network for A/D and D/A conversion utilizing a feedback amplifier is described. The two-stage weighted capacitor DAC requires a smaller range of capacitor values then the conventional weighted capacitor DAC and is not subject to the nonlinear effects of parasitic capacitance. Experimental results of such a DAC implemented using a conventional n-channel metal-gate MOS process are presented. A discussion of the comparative accuracy and area of one- and two-stage weighted capacitor DAC's on the basis of capacitor tracking is given.

72 citations


Patent
30 Jul 1979
TL;DR: In this paper, a microcomputer is used to control the basic key intersection scanning and for accurately calibrating and adjusting the sensing threshold of the sense amplifier prior to testing each key intersection so that the effects of stray impedance and varying voltage levels may be compensated for.
Abstract: A sensing apparatus for detecting impedance changes in a variable impedance matrix keyboard. A microcomputer is utilized to control the basic key intersection scanning and for accurately calibrating and adjusting the sensing threshold of the sense amplifier prior to testing each key intersection so that the effects of stray impedance and varying voltage levels may be compensated for. The micro computer supplies sense amplifier sensitivity threshold selection address codes to set the sensing level for the amplifier. Trial drive pulses are applied to a reference capacitor and are gated to the sense amplifier while the sensing level thereof is varied until no output is obtained. This effectively adjusts the sensing circuits for variable voltage power fluctuations occurring over a short time and compensates for variable capacitive effects not associated with actual key switch movements. The micro computer also has a memory containing known stray capacitance values associated with a given keyboard design and these values are also used to compensate by modifying the sensing threshold above or below the calibrated sensing level achieved. Thisis done after driving and measuring the capacitance response until a zero output is obtained so that the sensing level may be individually set for each given key in the matrix at that precise level which can provide the highest non-saturating sensitivity level for the amount of stray capacitance known to be associated with the key and for the existing power and capacitance conditions as originally determined by checking the reference capacitor.

48 citations


Patent
04 May 1979
TL;DR: In this article, the presence of particles of combustion in the ambient environment results in a change in the dielectric constant of the sample capacitor, thus changing its capacitance, which is detected by an oscillator in the sample circuit, the mismatch of oscillators in the two circuits causing an exclusive OR-gate to go high, activating an alarm system.
Abstract: A capacitive shift fire detection device having a sample circuit and a reference circuit, each circuit having an air capacitor connected to an oscillator and a counter. The presence of particles of combustion in the ambient environment results in a change in the dielectric constant of the air dielectric of the sample capacitor, thus changing its capacitance. This change in capacitance is detected by an oscillator in the sample circuit, the mismatch of oscillators in the two circuits causing an exclusive OR-gate to go high, activating an alarm system.

23 citations


Journal ArticleDOI
TL;DR: In this article, a beam-lead Mott Schottky-barrier mixer with a zero-bias junction capacitance near 10 fF, very low parasitic capacitance, ideality factor near or below 1.07, and a zerobias cutoff frequency as high as 5000 GHz has been developed.
Abstract: A novel GaAs beam-lead Mott Schottky-barrier mixer device having a zero-bias junction capacitance near 10 fF, very low parasitic capacitance, ideality factor near or below 1.07, and a zero-bias cutoff frequency as high as 5000 GHz has been developed. The diode configuration makes use of a unique design in which the current distribution in the N+ layer at d.c. and at r.f. are equivalent, and thus, for the first time, it is possible to fully characterise mixer devices at d.c. Samples of these devices have been tested at 94 GHz in a broadband fin-line mixer structure, and realised a mixer conversion loss below 6.0 dB. This performance is representative of the best results achieved to date in a printed-circuit mount.

16 citations


Patent
09 Jul 1979
TL;DR: In this article, a charge transfer analog-to-digital converter is provided with means to establish the potential across a large storage well at a comparator threshold voltage at the initiation of a cycle.
Abstract: A charge transfer analog-to-digital converter is provided with means to establish the potential across a large storage well at a comparator threshold voltage at the initiation of a cycle. Charge transfer circuitry is also provided for transferring, into the large potential well, charge packets of size dependent only upon the value of a charge packet capacitance and a scaling voltage. Parasitic capacitance effects are essentially eliminated.

14 citations


Patent
07 Jun 1979
TL;DR: In this paper, the authors proposed a generator for the starting and thereafter maintaining energization and operation of a load which has a relatively high impedance during starting and a substantially lower impedance after starting and during operation thereof.
Abstract: A generator for the starting and thereafter maintaining energization and operation of a load which has a relatively high impedance during starting and a substantially lower impedance after starting and during operation thereof. The load may be an ionic conduction lamp including a phosphor excitable lamp in the nature of a fluorescent lamp, or electroluminescent lamp, or vapor lamp. The generator includes a mechanism for generating electrical power with a relatively high voltage and impedance so as to match the relatively high impedance of the load before starting and generization of electrical power of a substantially lower voltage and impedance so as to match the lower impedance of the load during the energizing and operation of the load. The mechanism for generating the electrical power may be an inductive member, such as a coil, and a solid state element, such as a transistor, to develop a voltage over the coil. The coil may be coupled to the lamp through some agent developing a capacitance, e.g., a conductor with a capacitor or stray capacitance between the lamp and the coil. Further a tap intermediate the ends of the coil may be coupled to the load. The capacitance which couples the generator to the lamp before starting is effectively electrically inoperable and out of the circuit after starting of the load. The agent developing the capacitance is located such that the full voltage developed across the coil is delivered to the load during starting, but after starting and during operation only a portion of the voltage developed between one terminal and the tap of the coil is used to drive the load. The generator thereby eliminates the need of a conventional ballast and starting mechanism. In this way, energization of the lamp can be maintained with substantial energy savings compared to prior art ballasts used with ionic conduction lamps. Further energy savings are achieved by generating current and voltage pulses for operating the lamp where the voltage pulses have a greater decay rate to a zero level than the current pulses which have a more gradual decay. Thus, the lamps may be driven by an electric signal where the current pulses are driven by a substantially reduced voltage level for a substantial period of time.

12 citations


Journal ArticleDOI
TL;DR: In this paper, a beam lead GaAs Schottky-barrier mixer diode with high performance has been developed for use in super high frequency (SHF) receiving system.
Abstract: A novel beam lead GaAs Schottky-barrier mixer diode with high performance has been developed for use in super high frequency (SHF) receiving system. The parasitic capacitance of the diode has been reduced to 0.03 pF by using thick polyimide insulating film formed by improved etching techniques. The series resistance has been lowered to 0.5 Ω by a liquid-phase double epitaxial method of growing an n-n++active layer on an n+wafer. The total diode capacitance at zero bias has been lowered to 0.15 pF using a 10-µm junction diameter. An n factor of less than 1.10 was obtained. The calculated cutoff frequency including parasitic capacitance exceeds 2000 GHz. Several reliability tests including temperature cycling in high humidity show good results. In an SHF downconverter consisting of a waveguide which contains a planar circuit, the diode was attached to the planar circuit by means of an intermediate plate, despite the small diode dimensions of 0.75 mm by 0.22 mm. An overall noise figure (NF) as low as 4.3 dB, and conversion loss as low as 3.0 dB were achieved at 12 GHz (IF range of 290-470 MHz and IF amplifier NF of 1.5 dB). These values are shown to be satisfactory for application to a low-noise receiving system for satellite TV broadcasting.

11 citations


Patent
27 Sep 1979
TL;DR: In this paper, a system for interfacing a SWIF with a tuner and an amplifier in the IF section of a television receiver is described, where the output of the SWIF is coupled to an amplifier which has a low, untuned input impedance to establish a mismatch between SWIF and the amplifier to therey reduce triple-transit effects associated with SWIF.
Abstract: A system is described for interfacing a SWIF with a tuner and an amplifier in the IF section of a television receiver. In the preferred arrangement, the tuner is coupled to the input of the SWIF so as to efficiently transfer signal power to the SWIF over the frequency range of the tuner's output. The output of the SWIF is coupled to an amplifier which has a low, untuned input impedance to establish a mismatch between the SWIF and the amplifier to therey reduce triple-transit effects associated with the SWIF. Preferably, the amplifier is a common-base amplifier whose input impedance is defined by a real impedance component which is substantially smaller in magnitude than its reactive impedance component. Hence, the real component of the amplifier's input impedance is dominant and the effects of stray capacitance between the SWIF and the amplifier are reduced.

8 citations


Patent
13 Aug 1979
TL;DR: In this paper, a high voltage clock generator including an isolation and precharge circuit is used to charge a bootstrap capacitance at a time prior to driving the load capacitance to a higher voltage level.
Abstract: A high voltage clock generator including an isolation and precharge circuit to charge a bootstrap capacitance at a time prior to driving the load capacitance to a higher voltage level. The first clock generator charges a load capacitance to the initial voltage level while the isolation precharge circuit has already acted to charge the bootstrap capacitance. A second clock generator drives the bootstrap capacitance to a higher voltage level, at which time the isolation precharge circuit acts to engage the bootstrap capacitance to the load capacitance and charge the load capacitance to a higher voltage level.

7 citations


Proceedings ArticleDOI
01 Jan 1979
TL;DR: The base emitter self-aligned technology (BEST) as discussed by the authors was developed as a practical method to increase the packing density of bipolar LSIs and to realize high speed when operated at low power.
Abstract: Base Emitter Self-aligned Technology (BEST) as developed as a practical method to increase the packing density of bipolar LSIs and to realize high speed when operated at low power. The BEST technology applies a selective oxidation technique on poly silicon. It produces a smaller device and reduces the circuit parasitic capacitance. An experimental low power CML 29-stage ring oscillator was made using BEST. Propagation delay time of 0.65 nanoseconds per gate was obtained at a power dissipation per gate of 0.6 milliwatts.

7 citations


Journal ArticleDOI
M. Isobe1, Jun Iwamura, M. Ohhashi, H. Koike, Kenji Maeguchi, Tai Sato, Hiroyuki Tango 
TL;DR: An n-channel MOS LSI microprocessor integrating 20 000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process as mentioned in this paper.
Abstract: An n-channel MOS LSI microprocessor integrating 20 000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account. It is verified that a) the observed yield of a very large SOS chip is higher than the value predicted from a randomly distributed defects model, and b) the yield-sensitive active area of an SOS is so small that it can compensate for the yield degradation due to the very large defects density on an SOS wafer.

Patent
19 Mar 1979
TL;DR: In this paper, a diode is connected in series between a touch sensitive capacitive network and wiring for connecting the touch sensitive network to the control unit, and a filter capacitor is connected with the diode to charge the filter capacitor to the peak amplitude of a predetermined portion of the alternating signal.
Abstract: User control apparatus for controlled systems includes a touch sensitive capacitive network for changing the amplitude of an alternating signal when contacted by a user and a control unit for controlling a predetermined function of the controlled system in response to a control signal representing amplitude changes of the alternating signal. A diode is connected in series between the touch sensitive capacitive network and wiring for connecting the touch sensitive capacitive network to the control unit. A filter capacitor is connected in shunt with the diode. The diode is poled to charge the filter capacitor to the peak amplitude of a predetermined portion of the alternating signal and also isolates the touch sensitive network from the capacitance of the filter capacitor and any stray capacitance associated with the wiring which may adversely affect the sensitivity of the touch sensitive capacitive network. When utilized in a television receiver, the alternating signals advantageously comprise pulses generated during deflection retrace intervals when the receiver's electron beams are normally blanked to reduce the visible effects of signals radiated from wiring between the source of alternating signals and the touch sensitive capacitive network.

Patent
David D. Thornburg1, Brian Rosen1
29 May 1979
TL;DR: In this paper, a tri-state capacitance controlled keyswitch with a deformable concave electrode moveable by means of an actuator toward and away from a pair of capacitor plates underlying a dielectric layer is described.
Abstract: A tri-state capacitance controlled keyswitch having a deformable concave electrode moveable by means of an actuator toward and away from a pair of capacitor plates underlying a dielectric layer in order to change the capacitive coupling between the capacitor plates. The electrode is normally remote from the dielectric layer in a weak capacitance open circuit position, a first higher capacitance closed circuit position exists when the electrode is undeformed and is in contact with the dielectric layer, and a second highest capacitance closed circuit position exists when the electrode is deformed and is in contact with the dielectric layer.

Patent
05 Sep 1979
TL;DR: In this article, a substrate bias generating circuit capable of obtaining a bias voltage effective for an improvement of the operational speed and a reduction of the power consumption, by paying attention to that substrate bias of more than 5V was effective for a reduction in parasitic capacitance.
Abstract: PURPOSE:To construct a substrate bias generating circuit capable of obtaining a bias voltage effective for an improvement of the operational speed and a reduction of the power consumption, by paying attention to that substrate bias of more than -5V be effective for a reduction of parasitic capacitance. CONSTITUTION:The construction is made by a first pulse smoothing circuit (MIS diode Q1, condenser C1), a second pulse smoothing circuit (MIS diode Q2, condenser C2) and MIS diode Q2, with a gate and drain connected by connecting the source to the connection point of a MISFET Q2 and the diode Q2, that is an output point of the second pulse smoothing circuit. In such circuit construction, the output bias voltage VBB is obtained at the drain of the MISFET Q2.

Proceedings ArticleDOI
W. Cady1, S.P. Yu
01 Jan 1979

Patent
14 Jul 1979
TL;DR: In this paper, the authors used the adjusting package of the shape as the upper package to adjust the resonant frequency of the crystal oscillator supporting the crystal chip with elastic member.
Abstract: PURPOSE:To avoid the change in the parasitic capacitance for resonance frequency adjustment and after mounting, by using the adjusting package of the shape as the upper package, in adjusting the resonant frequency of crystal oscillator supporting the crystal chip with elastic member. CONSTITUTION:The elastic member 5 supporting the drystal chip 6 is formed with the adjusting package 9 so that it can not be removed. This adjusting package 9 is formed as the same shape as the upper package when it is mounted with cold pressing, and it has the evaporation hole 10 at approximately the center of the electrode film 7. When the metal is evaporated from the direction shown in the arrow to adjust the resonant frequency, the evaporation metal raches the electrode film 7 through the evaporation hole 10 and the resonant frequency of the crystal chip 6 decreases. In this case, oscillation is made with the oscillation circuit, and the evaporation is stopped when it raches desired oscillating frequency by comparing the oscillated frequency with the reference frequency. Next, the adjusting package 9 is picked up and mounting is made with the method such as cold pressing by attaching the upper package of the same shape. Thus, the parasitic capacitance can be unchanged at resonant frequency adjustiment and after mounting.

Patent
23 Feb 1979
TL;DR: In this paper, an ion implantation was used to establish MIS semiconductor device small in size, less in parasitic capacitance, and excellent in ohmic contactness with wiring materials.
Abstract: PURPOSE:To establish MIS semiconductor device small in size, less in parasitic capacitance, and excellent in ohmic contactness with wiring materials, by forming the source and drain through using ion implantation.

Patent
22 Sep 1979
TL;DR: In this paper, the static type memory cell circuit is constituted with the driver transistors Q1, Q2, load depletion type transistorsQ3,Q4, and transfer gate transistors q5,Q6.
Abstract: PURPOSE:To reduce the delay time and to speed up the operaton, by providing two FET's on one semiconductor substrate and using the FET having the gate electrode controlled lower resistance wiring as transfer gate. CONSTITUTION:The static type memory cell circuit is constituted with the driver transistors Q1, Q2, load depletion type transistors Q3,Q4, and transfer gate transistors Q5,Q6. Further, the selection of memory cell is made with the digit lines L2 and L3 taking the data in the cell via transistors Q5, Q6 and the word line L1 connecting the gates of the transistors Q5, Q6. With this constitution, the gate electrodes of transistors Q5, Q6 are formed with Al wire excellent in conductivity and the gates of Q1 to Q4 are formed by using polycrystal Si. Thus, since the layer resistance of the Al wire can be decreased to about 0.02 ohm/square, the stray capacitance of the word line L1 can rapidly be charged and discharged and the circuit is of high speed type.

Patent
09 Aug 1979
TL;DR: In this paper, a complementary MOSFET amplifying circuit which is not subject to the effect of the dispersion in the circuit constant and has excellent frequency response is presented.
Abstract: PURPOSE:To establish complementary MOSFET amplifying circuit which is not subject to the effect of the dispersion in the circuit constant and has excellent frequency response. CONSTITUTION:By simultaneously manufacturing two elements with the same manufacturing process, the DC bias current ratio between MOSFET Q1 and Q3 and that for MOSFET Q2 and Q4 are in agreement with each other at a higher accuracy, and even if there is a change in the manufacturing conditions of semiconductor integrated circuits, the bias point of the output terminal OUT is set to a suitable value. Further, since no resistance and stray capacitance with decreases high frequency performance are present between the drain of amplifying MOSFET Q3 and Q4 and the output terminal OUT, greater voltage gain can be given even at higher frequencies.

Journal ArticleDOI
TL;DR: In this paper, a series of high-voltage probes with a high input impedance (≳ 10 kΩ) and good frequency response (≲ 100 MHz) have been built.
Abstract: A series of high-voltage probes (≃300 kV) with a high input impedance (≳ 10 kΩ) and good frequency response (≲ 100 MHz) have been built These probes use two concentric cylinders of resistive material; the inner cylinder is the larger resistor of a voltage divider and the outer cylinder shields the inner one from the stray capacitance which would normally degrade the response These cylinders can be made of almost any resistive material provided that certain theoretical considerations based on nonuniform field penetration and probe impedances are taken into account The theories discussed are compared to the experimental results of several probes with different resistive materials and relative dimensions Of primary interest are the probe's response, cost, weight, construction time, energy absorption, and system compatability (loading and shielding)

Patent
18 Jan 1979
TL;DR: In this paper, the authors propose to increase the performance at high frequencies with less parasitic capacitance and increase the mutual conductance by reducing lines of electric force at the distance between the gate region and the source region through the reduction of the width for those.
Abstract: PURPOSE:To increase the performance at high frequencies with less parasitic capacitance and to increase the mutual conductance, by reducing lines of electric force at the distance between the gate region and the source region through the reduction of the width for those.

Patent
15 Aug 1979
TL;DR: In this paper, the authors proposed a method to supervise an insulation lowering of an electrical route discriminating an alternating current component and a direct current component by applying a directcurrent voltage to a circuit flowing a charging current, supervising an insulation state of the electrical route with this direct current voltage and by flowing a current flown through a stray capacitance through a condenser.
Abstract: PURPOSE:To supervise an insulation lowering of an electrical route discriminating an alternating current component and a direct current component by applying a direct current voltage to a circuit flowing a charging current, supervising an insulation state of the electrical route with this direct current voltage and by flowing a current flown through a stray capacitance through a condenser CONSTITUTION:Making an insulation resistance supervising value of an electrical route to be RA, a supervising voltage of a direct current power source 20 of a constant voltage E, a resistance value of a detecting resistor 6 R6, a sum of series resistance looking from an above mentioned direct current power source 20 such as current limitting resistors 5 and 14, a grounding resistance value at a ''B'' point etc to be RB, then a voltage E6 appearing at both ends of the detecting resistor 6 becomes to be E6=R6 E/(RA+RB+R6), supervising a value of E6 corresponding with a variation of RA, detecting after comparing with a determined value at a comparator 72, only when reaching to a determined value a time limitting circuit 73 and a switching circuit 74 are operated and an electromagnetic device 8 is driven

Journal ArticleDOI
M. Isobe1, Jun Iwamura, M. Ohhashi, H. Koike, Kenji Maeguchi, Tai Sato, Hiroyuki Tango 
TL;DR: An n-channel MOS LSI microprocessor integrating 20000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process as mentioned in this paper.
Abstract: An n-channel MOS LSI microprocessor integrating 20000 transistors on a chip has been realized on a sapphire substrate utilizing the Coplanar-II process. It contains ALU, shifters, and 44 registers which are combined to three 16-bit buses. By utilizing three types of threshold voltage for load transistors, 28-percent reduction in power dissipation is achieved. The minimum cycle time is 200 ns. By using the Coplanar-II process, anomalous leakage currents due to parasitic transistors at the sides of island are suppressed. It is found that the silicon-on-sapphire (SOS) version operates 2.3 times faster than the bulk-silicon version, which is mainly explained by the parasitic capacitance ratio. Parallel-plate approximation in calculating a wiring capacitance results in an underestimate by a factor of 60 compared with taking the two-dimensional effect into account.

Patent
16 Mar 1979
TL;DR: In this paper, the authors proposed to establish the transistor less in parasitic capacitance, by taking the constitution that the semiconductor layer causing parasitic capacitive capacitance is removed, by removing it from the transistor.
Abstract: PURPOSE:To establish the transistor less in parasitic capacitance, by taking the constitution that the semiconductor layer causing parasitic capacitance is removed.

Patent
21 Jun 1979
TL;DR: In this article, a conductive glass film is formed over the entire emitere surface to obtain stabilizing resistances of the structure of a small parasitic capacitance, which enables stabilizing resistor to be evenly distributed to the entire surface of the emitter layer.
Abstract: PURPOSE:To obtain stabilizing resistances of the structure of a small parasitic capacitance by forming a conductive glass film evenly over the entire emitere surface. CONSTITUTION:A SnO2 layer 11 having a suitable resistivity and thickness and a SnO2 layer 11' having an extremely low resistivity are laminated on a wafer formed with base connection layers 8. Next, a SiO2 film 5 is selectively formed and the films 11', 11 are etched away. Thereafter, electrodes are formed in an ordinary manner. This method enables stabilizing resistances to be evenly distributed to the entire surface of the emitter layer 4 and this structure does not increase the parasitic capacity between the emitter and collector.

Patent
Goerth Joachim Dipl Ing1
15 Feb 1979
TL;DR: In this article, the authors proposed an approach to reduce parasitic capacitance between the MOS capacitance and the semiconductor substrate by placing a terminal electrode on the first semiconductor layer.
Abstract: The semiconductor element forms an integrated circuit and consists of a substrate with on opposite conductivity semiconductor layer, coated with an insulating film. On the latter is provided a second conductive layer, between which and a highly doped second conductivity zone, which bounds the surface of the first semiconductor layer(2), is formed a MOS capacitance. Underneath the highly doped zone (3) in the first semiconductor layer is provided a surrounding zone (10) of the conductivity, which is pref. provided with a terminal electrode (4). A further terminal electrode (12) may be arranged on the first semiconductor layer. This arrangement reduces parasitic capacitance between the MOS capacitance and the semiconductor substrate, without any further measures.

Patent
23 Apr 1979
TL;DR: In this paper, the coupling plate was placed between the primary and secondary tuning circuits and variable the opposing area and distance of the coupling plates so that the degree of coupling can be adjusted.
Abstract: PURPOSE:To establish the coupling circuit suitable for mass-production, by placing the coupling plate between the primary and secondary tuning circuits and by making variable the opposing area and distance of the coupling plate so that the degree of coupling can be adjusted CONSTITUTION:The opposing primary coil 23 and secondary coil 24 are placed via the separating plate 22 separating about 1/2 of the internal of the console 21 The variable air capacitors 25 and 26 are connected to the coils 23 and 24 without separating plate, forming the tuning circuits 31, 32 for the primary and secondary The coupling plates 27 and 28 are placed on the capacitors 25 and 26, and one end of the coupling 27 is slightly projected to the secondary capacitor 26, one end of the coupling plate 28 is projected to the primary capacitor 25 and setting is made so that the end of the coupling plate 27 is opposed to the plate 28 parallelly The stray capacitance of the primary and secondary side is determined with the area and the distance of the opposing part of the coupling plates 27 and 28 and the coupling degree can be determined, then the degree of coupling can easily be adjusted and coupling circuit suitable for mass-production can be established

Patent
11 Jul 1979
TL;DR: In this paper, the minimum unit used for telephone exchangers is 1 point, which is constituted with the two switch circuits, one drive circuit and four protection circuits, constituting the cross point chip 11 of 1 point.
Abstract: PURPOSE:To prevent the interferrence between switch circuits and to increase the degree of integration with short connection wirings, by locating separately one set of switch circuits via the driving circuit or protection circuit placed adjacently. CONSTITUTION:The minimum unit used for telephone exchangers is 1 point, which is constituted with the two switch circuits, one drive circuit and four protection circuits. With this constitution, so as not to close the switch circuit 2A and 2B, the drive circuit 9 and the protection circuits 10A and 10B constituted two sets one pair are located around them, constituting the cross point chip 11 of 1 point. To constitute the switch so, in the island of single crystal Si isolated and separated with SiO2 film and polycrystal Si, it can be formed for the functional element of each circuit. Thus, the wiring among circuits can be made shortest and the parasitic capacitance caused under the wirings is reudced so that it can not give any effect on the switching performance.

Patent
25 Jul 1979
TL;DR: In this article, the authors propose to discharge the charge in the stray capacitance of delivery line cable positively and remove the undesired result due to the charge to enable stable information delivery.
Abstract: PURPOSE:To enable stable information delivery, by discharging the charge in the stray capacitance of delivery line cable positively and removing the undesired result due to the charge. CONSTITUTION:The receiver 10 has the constant current circuit 11 flowing a given current I to the receiver input terminal. When the DC pulse of amplitude E1 is delivered, the receiving voltage E5 of the receiver 10 is E5=E1-Z1I. When the charge Q=CE5 (where: C is stray capacitance) is discharged with a given current I, the reception voltage E5 is decreased linearly with a given slope as shown in Fig. B, and the voltage is zero after time t4. Since the time t4 can be determined smaller than the read-in pulse period t3 the trailing length of reception voltage can be reduced than conventional length, preventing misrecognition of information.

Patent
07 Sep 1979
TL;DR: In this paper, a comparison detection circuit is proposed to establish the comparison circuit which can not cause malfunction from the effect of the stray capacitance of the signal lines through which the counter output of the counter circut is delivered.
Abstract: PURPOSE:To establish the comparison detection circuit which can not cause malfunction from the effect of the stray capacitance of the signal lines through which the counter output of the counter circut is delivered. CONSTITUTION:The signals q1 to q3 before a half bit shift for the counter output signals Q1 to Q3 of counter circuit 21 counting sequentially the clock pulse phi supplied and the bit data LD1 to LD3 preset are compared 44 each other. Further, this comparison signal is shifted 48 in a half bit of the clock pulse phi, so that the ''1'' level signal of the pulse length less than a half bit of the clock pulse phi established in the comparison signal can not be detected. Thus, the coincidence signal is established only when the number of count is in agreement with the number of counts expressed in the bit data LD1 to LD3 preset, therefore no malfunction can not be caused independently of the value of stray capacitance of the delivery signal lines.