Showing papers on "Parasitic capacitance published in 1982"

A simple formula for the estimation of the capacitance of two-dimensional interconnects in VLSI circuits

Abstract: A simple formula for the estimation of the capacitance of a single interconnection line in VLSI circuits is presented It is shown that the approximation agrees favorably with the results obtained from much more costly two-dimensional simulations The approximation is also simpler and more accurate than other approximations that have been proposed

Switched capacitor DSB modulator/demodulator

Abstract: An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90° phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc. The amplifier and feedback capacitors combine the charge signals for producing a single-sideband signal on A1's output terminal. This circuit is converted to a balanced modulator by omitting C5 and C6. In an alternate embodiment of a single sideband modulator that requires only a pair of switched capacitors C11 and C12, a 4-phase switch means alternately charges C11 and C12 with associated ones of the quadrature-phase input signal voltages while alternately connecting C12 and C11 as feedback capacitors across A1, the polarity of each capacitors feedback voltage being reversed each time that capacitor is connected across the amplifier. This circuit is operated as a balanced modulator by omitting one of the capacitors.

VLSI parasitic capacitance determination by flux tubes

Abstract: A two-dimensional numerical approach for calculating capacitance between two conductors through different dielectrics is developed. The approach uses Laplace's equation in two dimensions to determine potentials on a grid system between the conductors. Equipotential lines are generated using these potentials and curvilinear squares can be formed to construct the flux tubes between the conductors. The application of Gauss's law to these potentials provides the charge on a conductor and results in the determination of capacitance values.

Semiconductor memory with selectively enabled precharge and sense amplifier circuits

Abstract: Bit line precharge circuits, sense AMP circuits and input-output line precharge circuits are respectively divided into two groups by select circuits which are controlled by a select control signal. Only the selected precharge circuits and the sense AMP circuits are enabled before a readout operation. The peak current for precharging bit lines is reduced to one-half as compared to conventional circuits due to the decrease of stray capacitance to be precharged.

Solid state transmission gate

Abstract: A solid state transmission gate having a low "on" resistance utilizes capacitive devices for partially compensating parasitic capacitance effects, a P-channel device and an N-channel device with a switched tub or substrate to compensate for parasitic capacitance effects When the transmission gate is conducting, the tub or substrate of the N-channel device is switched from one of its current electrodes to a reference potential such as ground Before the transmission gate is opened electrically, a settling time is provided to allow charge which is coupled from parasitic capacitance to settle

Measurement of intrinsic capacitances of MOS transistors

Abstract: An electrometer/coulombmeter circuit technique to measure capacitance characteristics of the MOS transistor will be discussed. Experimental data for substrate capacitances, non-reciprocal elements and non-quasi-static effects, compared to theory, will be presented.

Voltage-controlled oscillator having three or more varactor diodes

Abstract: In a voltage-controlled oscillator having an LC resonant circuit including a varactor circuit so that resonant frequency is controlled by a D.C. bias or control voltage applied to the varactor circuit, three or more varactors are connected in series in one embodiment so that a high-frequency voltage applied to the varactor circuit is divided into a plurality. The varactors may be connected in the same direction or opposite direction. In another embodiment, a plurality of series circuits of varactors are connected in parallel to provide the varactor circuit, where each series circuit comprises two or more varactors. A series-parallel connection of a plurality of varactors may be arranged in a matrix. In order to reduce undesirable stray capacitance, some or all varactors are attached to a printed circuit board so that they are normal to the plane of the printed circuit board. In one embodiment an auxiliary printed circuit board is employed so that some varactors are spaced from a main circuit board. The voltage-controlled oscillator of the invention shows high carrier-to-noise ratio throughout a wide frequency range.

A Description of MOS Internodal Capacitances for Transient Simulations

Abstract: Charge versus voltage and internodal capacitance versus voltage characteristics are calculated for a short-channel MOSFET using a unified model of the dc device behavior. Velocity saturation is an important feature in the results. The importance of charge and capacitance calculations is assessed using a high speed MOS transient simulation. Device current and gate charge are determined to be the important ingredients for accurate simulation.

Real-time programmable low power SC bandpass filter

Abstract: A real-time programmable switched capacitor (SC) second-order bandpass filter is presented. It is based on the voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and, therefore, it is insensitive to the parasitic capacitances between the bottom plate of the implemented MOS capacitors and the substrate. The circuit offers digital programming capability (two Q factors and three center frequencies) and low power dissipation (185 /spl mu/W at a sampling frequency of 8 kHz and with a power supply voltage of 10 V). The filter has been integrated in CMOS metal-gate technology.

On-chip capacitance measurement circuits in VSLI structures

Abstract: A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.

Gigabit logic operation with enhancement-mode GaAs MESFET IC's

Abstract: Enhancement-mode GaAs MESFET IC's have been fabricated using electron-beam lithography A recessed-gate structure to reduce the gate-to-source resistance and an air-bridge overlay interconnect to reduce stray capacitance were employed A 30-ps delay time with an associated power dissipation of 19 mW is obtained with a 06 × 20-µm gate GaAs MESFET, which is the highest speed among the GaAs FET logics Divide-by-eight counter has exhibited a 38-GHz maximum clock frequency with a power dissipation of 12 mW/gate

Resistance and capacitance measuring device

Abstract: This circuit measures both the resistance and the capacitance of the parallel RC circuit that is the equivalent of any substantially non-inductive two-port device. Thus, the circuit can measure any resistance, capacitance, RC network, or diode, including photovoltaic diodes. The invention uses an operational amplifier, an audio A.C. oscillator and a voltage measuring device such as a digital RMS voltmeter. The resulting apparatus is small, inexpensive, accurate, and easy to operate. The resistance is measured with the audio oscillator set for a low frequency (such as 70 Hz); the capacitance is measured when the audio oscillator is set at a high frequency (such as 20 KHz). The resultant values can either be calculated using simple formulas or can be displayed directly using an analog or digital circuit.

Switched capacitor feedback sample-and-hold circuit

Abstract: The feedback sample-and-hold stages of a transversal filter bank include a primary sample-and-hold branch and a secondary sample-and-hold branch for correction of offset voltage in the primary branch which results from switching charge feedthrough of its sampling switch. A pair of N-channel buffer transistors, one an enhancement type and one a depletion type, are so connected to the branches that power supply noise is attenuated. Additionally, the parasitic capacitance of the enhancement transistor acts as a coupling capacitor for the correction function.

A new VLSI memory cell using capacitance coupling

Abstract: A new VLSI memory cell, which offers small cell area, about 6F2(where F is the feature size), internal cell gain and high alpha-particle immunity is proposed. Since it employs capacitance coupling in a write operation, it requires only one bit line and is called a Capacitance-Coupling (CC) cell. A CC cell consists of three transistors and a capacitor, which are integrated in a small area by sharing their nodes with one another. The charge is stored in a P+-type diffused layer in a shallow N-type diffused layer. The P+-layer potential controls the readout current which flows through the N-layer. Experimental test devices having a 0.7 \micro m deep N-layer and 0.2 \micro m deep P+-layer were fabricated. The complete CC cell operation was confirmed.

Common-gate GaAs FET design for monolithic microwave integrated circuits

Abstract: In order to provide low and exactly repeatable common lead inductance (gate lead inductance) and low feedback parasitics in a common-gate low noise amplifier, a GaAs FET connects the gate electrode to ground at various points along its width by means of an air bridge crossover structure. This structure crosses over the input (source) lines with very low capacitance. Since the gate lead inductance is low in this design, and because in monolithic form this inductance does not vary as is the case for a device grounded using bond wires, common-gate circuit stability is assured. This device preferably uses the well-known pi-gate configuration to provide low drain-gate parasitic capacitance and equal phasing to all parts of the device.

EDM Method and apparatus with a continuous DC supply using stray gap capacitance to trigger discharge

Abstract: An EDM method and apparatus in which a continuous DC voltage is applied across the EDM gap via a first switch held conductive, and a stray capacitance distributed in the supply circuit including the EDM gap is recurrently charged and discharged to produce successive electrical discharges between the tool electrode and the workpiece. A gap sensor monitors the magnitude of high-frequency signals contained in the successive discharges and, when the sensed magnitude falls below a threshold level, provides a trigger signal which is used to turn on a second switch connected across the EDM gap in parallel with the DC source to short-circuit the EDM gap, thereby terminating the successive discharges. The conducting second switch serves to discharge the residual charge on the stray capacitance and prevents charge build-up thereon. Then the first switch may be turned off. The time interval in which the gap is free from current flow continues until the first switch is turned on following the turn-off of the second switch. The cycle is repeated.

Electrically programmable read only memory having reduced leakage current

Abstract: An electrically programmable read only memory includes a plurality of non-volatile memory elements having control gates which are commonly connected to a first word line and drains which are coupled to a write-down circuit for supplying a write-down voltage to said drains. To prevent the flow of leakage current caused by parasitic capacitance, at least one of source electrodes of the plurality of non-volatile memory elements is connected to ground potential through the drain-source path of a first switch MISFET whose gate electrode is connected to the first word line. When a word line driving signal of non-selection level is applied to the first word line, the first switch MISFET is non-conductive. Thus, leakage current is prohibited from flowing through the first switch MISFET. Further, in order to prevent deterioration of the rewrite-down efficiency of the memory, the write-down circuit includes a pn-junction element having a junction characteristic which is substantially equal to the drain junction characteristic of the non-volatile memory elements. The level of a write-down voltage to be applied to the drains of the non-volatile memory element is determined on the basis of the reverse breakdown voltage of the pn-junction element. Thus, the breakdown of the drain junction of the non-volatile memory elements during a write-down operation can be prevented, so that deterioration of the rewrite-down efficiency of the electrically programmable read only memory can be prevented.

Liquid crystal matrix display devices

Abstract: A liquid crystal matrix display device has a plurality of liquid crystal display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to compensate for crosstalk that occurs because of parasitic capacitance between the vertical transmitting lines and the liquid crystal display elements, auxiliary lines are provided for the columns of such display elements, and each has a predetermined compensating capacitance relative to its associated liquid crystal display elements. A compensating signal, which is an inverted version of the video signal, is applied in succession to the auxiliary lines to compensate for any crosstalk.

Balancing compensation in differential amplifiers with a single-ended drive

Abstract: In a differential amplifier with single-ended drive in accordance with the invention a balancing impedance (20 and 28 respectively) is arranged between the base of the transistor (3 and 22 respectively) connected to the signal input (1 and 21 respectively) and the common point (9) of the two emitters of the transistors (3, 4 and 22, 23 respectively), which form a differential pair. The capacitance value of the capacitor (20 and 28 respectively) which forms at least part of the balancing impedance is at least substantially equal to the capacitance value of the stray capacitance (19 and 27 respectively) of the collector-substrate (or "earth") junction of the transistor (10) which forms the current source. This results in a symmetry of the capacitances between the input (1 and 21 respectively) and the common point (9) and between the common point (9) and earth via the transistor (10) forming the current source, which yields an improved balance in the output signals on the output terminals (5, 6) and 30, 31 respectively) and a flat frequency response of the differential amplifier for higher frequencies.

Control circuit for electromagnetic devices

Abstract: In a control circuit, which has a current switching-over circuit including at least four switching transistors for controlling a current flowing through an electromagnetic device, the control circuit has driving circuits each of which drives the switching transistors in such a way that a short circuit does not occur during the switching-over operation thereof.

Tuning circuits with bendable U-shaped variable inductor for garage door actuators

Abstract: Tuning elements are provided for use in varying the inductance of the oscillatory circuits of the transmitter and receiver units of garage door actuators operating at ultra-high frequencies. Each oscillatory circuit is a closed loop circuit fabricated on a printed circuit board. The closed loop circuit comprises a pair of printed circuit conductive paths having a fixed capacitor connected across one of the ends thereof and a discrete generally U-shaped wire connected across the other of the ends thereof. The conductive paths and the U-shaped wire comprise the inductor of the oscillatory circuit. By bending the discrete U-shaped wire at its connections with respect to the plane of the printed circuit board, the inductance of the oscillatory circuit in each unit can be adjusted as needed so that they both operate at the same resonant frequency.

Vertical DMOS power field-effect transistors optimized for high-speed operation

Abstract: The optimization of planar vertical DMOS FETs for high-speed switching and amplification is discussed. Design considerations for a high-voltage device capable of sub-nanosecond switching are presented, and device layout and fabrication requirements for such a device are discussed. The fabrication sequence used to produce a high-speed vertical DMOS FET is then reviewed. Key features of the process include self-aligned polysilicon gates, fully implanted junctions, floating diffused guard rings, and gold-based metallization. The significant electrical characteristics of devices built with this process include drain-source breakdown (BVDSS) > 100 volts and common-source cutoff frequency (f co )= 2 GHz. Modelling of the dc and ac characteristics of short-channel DMOS devices is examined. Device performance in a test circuit shows that planar vertical DMOS is a good candidate for high-speed, high-voltage switching.

Switched capacitor balanced modulator/demodulator

Abstract: An integrated single-sideband modulator comprises six integrated capacitors C1-C6 and first switch means alternately connecting C1 and C2 as feedback capacitors across a differential input operational amplifier A1. The amplifier has a virtual ground potential on its inverting input terminal for causing it to operate as a voltage source and render the circuit relatively insensitive to parasitic capacitance effects associated with capacitor plates. Second switch means cooperates with A1, C1 and C2 and is responsive to 4-phase clock signals for driving input capacitors C3-C6 so as to convert first and second quadrature-phase input signal voltages into first and second electrical charge flow signals on the inverting input terminal that are a function of products of representations of the first and second voltages in switch state time intervals and associated pulse trains which have a 90° phase difference therebetween and a repetitive pattern such as +1, +1, -1, -1, etc. The amplifier and feedback capacitors combine the charge signals for producing a single-sideband signal on A1's output terminal. This circuit is converted to a balanced modulator by omitting C5 and C6. In an alternate embodiment of a single sidebank modulator that requires only a pair of switched capacitors C11 and C12, a 4-phase switch means alternately charges C11 and C12 with associated ones of the quadrature-phase input signal voltages while alternately connecting C12 and C11 as feedback capacitors across A1, the polarity of each capacitor's feedback voltage being reversed each time that capacitor is connected across the amplifier. This circuit is operated as a balanced modulator by omitting one of the capacitors.

Two-dimensional nature of diffused layers and certain limitations in scaling-down coplanar structure

Abstract: Limitation of the coplanar technology to geometry miniaturization has been investigated. Two-dimensional nature of diffused line capacitance in a coplanar structure is investigated for the first time delineating importance of the sidewall capacitance with decreasing feature size of devices. The effects of field channel-stop ion implantation on the narrow-channel effect, the field MOS threshold voltage, and the junction breakdown voltage are also discussed.

The development of millimetre wave mixer diodes

Abstract: A new format gallium arsenide beam lead diode has been developed which allows the total capacitance to be reduced sufficiently for applications throughout the millimetre waveband. The design involves the use of low melting point glass and has high mechanical strength for ease of handling. Metal-organic chemical vapour deposition has been used to provide the thin epitaxial layer required to minimize series resistance in the device. Typical measurements from many batches are total capacitance at zero bias 003 pF, including 002 pF stray capacitance, series resistance 6Ω and breaking force 4.5 g. The millimetre wave performance of the diodes has been demonstrated in microstrip mixer circuits operating at 90 GHz and 140 GHz. The microstrip single-ended mixer at 140 GHz extends the technology already established up to 100 GHz and includes a single crystal quartz substrate. The conversion loss of balanced mixers at 90 GHz is typically 6.5 dB and the single-ended mixer at 140 GHz displayed a loss of 7.0 dB.

PSK modem filter switch

Abstract: A PSK integrated circuit modem employs multi-mode filters in its switched capacitor circuitry for providing a plurality of filter response to accomodate a plurality of modem protocols. Each capacitor is selectively connected or disconnected from the circuit by a transistor switch, and selectively connected and disconnected from the circuit voltage reference by a transistor switch. The switches operate out of phase with each other so that when any capacitor is connected in the circuit, it is disconnected from the reference voltage and when any capacitor is disconnected from the circuit, it is connected to the reference voltage. The modem switch minimizes the effect of stray capacitance from the unselected capacitors and their associated transistor switches that have been turned off.

Semiconductor storing unit

Abstract: PURPOSE:To contrive speed-up of an EPROM by reducing the parasitic capacitance, by installing an NOR gate transistor between the memory cell and the power source. CONSTITUTION:Bit lines 131-13n are connected to power sources, respectively, through bit drivers Q1-Qn which are turned on and off in accordance with the output of outputs C1-Cn of column decoders, and an NOR gate having plural transistors Tr1-Trn which receive electric potentials at connecting points N1 -Nn of the bit drivers Q1-Qn and bit lines B1-Bn at their gate and forming a pre-sensing amplifier is provided. When this circuit configuration is used, electric potentials at bit lines which change depending upon the information stored in the memory cell, enter into the pre-sensing amplifier through T1, N1, Tr1, etc., and the parasitic capacitance becomes smaller than that of conventional circuit configurations. Therefore, speed-up of the EPROM can be realized.

Semiconductor integrated memory circuit

Abstract: A semiconductor integrated memory circuit in which bit line precharge circuits, sense amplifier circuits and input-output line precharge circuits are respectively divided into two groups by select circuits which are controlled by a select control signal. Only the selected precharge circuits and the sense amplifier circuits are enabled before a read-out operation. The peak current for precharging bit lines is reduced to one-half as compared to conventional circuits due to the decrease of stray capacitance to be precharged.

A stable and accurate current-comparator-based quadrature-current reference for power frequencies

Abstract: A current-comparator technique for obtaining a pure quadrature-current reference for power frequencies is described. The current in a solid dielectric capacitor of relatively high capacitance value or in an electronic inductor is compared, using the current comparator, to the current in a “lossless” gas-dielectric capacitor of relatively low capacitance value. The difference current derived from the output of the detection winding is added, through a feedback circuit, to the current in the solid dielectric capacitor or the electronic inductor resulting in a stable and pure quadrature current. The instability and loss angle of the quadrature current are not more than ±5 ppm and ±5 μrad, respectively. This quadrature current source is used to provide a reference current in an active/reactive power comparator bridge for calibration of active/reactive power meters.

Materials Considerations for Advances in Submicron Very Large Scale Integration

Abstract: Publisher Summary This chapter introduces the submicron metal-oxide semiconductor field-effect transistor (MOSFET) and examines the operation of submicron MOSFETs and junction field-effect transistor-metal semiconductor field-effect transistor (JFET-MESFETs). It presents the requirements for switching high-speed logic. It reviews the band structure variation for silicon and the relevant III-V compounds. The theory of random alloys and the band parameter variations, both for ternary and for quaternary alloys, is discussed. The comparison between silicon and various III-V technologies is drawn for devices in the extreme submicron region— that is, devices of 0.1-0.2 μm gate length. The chapter introduces the problem of line-to-line parasitic capacitance. For device sizes in the 0.12- μm or less region, the line-to-line parasitic capacitance begins to dominate the direct-line capacitance in setting the node capacitance. The chapter concludes that the devices fabricated from materials, such as gallium arsenide (GaAs) and indium phosphide (InP) offer definitive speed advantages over silicon circuitry. The ternaries and quaternaries offer no advantage over InP in comparable devices, and are severely restricted in packing density by their exceedingly poor value of thermal conductivity.