Showing papers on "Parasitic capacitance published in 1983"

Schottky diodes with high breakdown voltages

Abstract: The methods of increasing the breakdown voltages in silicon Schottky diodes is presented. In addition to a guarding ring, screen-diffusion regions were introduced. In this manner, the electrical field near the Schottky contact was lowered and, as a result, higher breakdown voltages were obtained. By using this method, the breakdown voltage can be increased by a factor of 3–5. However, a large device area is required for the same Schottky contact area and, therefore, the junction parasitic capacitance is greater.

Thin-film transistor circuit

Abstract: A thin-film transistor circuit used to drive a liquid crystal display (LCD) device is disclosed, which circuit includes a plurality of circuit components (C ij ) which are as arranged in the form of a matrix as to be connected with data lines (Y j , Y j+1 ) for supplying an image signal and with address lines (X i , X i+1 ) for supplying a gate pulse signal, whereby the circuit components control the picture element display in the unit picture element region of the LCD device. Each circuit component has a capacitor (26) connected to the unit picture element region (22) for temporarily storing the image signal, and a TFT transfer gate (20) having a gate electrode connected to one (X i ) of the address lines, a source electrode connected to one (Y j ) of the data lines, and a drain electrode connected to the capacitor (26). The transfer gate (20) performs the switching operation in response to the gate pulse signal, thereby transferring the image signal to the capacitor (26). A compensating pulse signal which is synchronized with the gate pulse signal and has a polarity opposite to that of the gate pulse signal is applied to the capacitor (26), thereby preventing a decrease in the image signal voltage across this capacitor (26) due to the parasitic capacitance component existing in the thin-film transistor (20).

Transition to chaos in a simple nonlinear circuit driven by a sinusoidal voltage source

Abstract: A circuit composed of a sinusoidal voltage source, a linear resistor, a linear inductor, and a diode in series is investigated. Subharmonic solutions of various orders have been found by computer simulations and there is evidence for the presence of chaotic solutions. The diode model used involves a nonlinear capacitor. The transition to chaos follows the same pattern as for iterated maps on an interval.

Semiconductor memory with an improved dummy cell arrangement and with a built-in error correcting code circuit

Abstract: In a read only semiconductor memory, signal lines such as data lines are subjected to an undesired parasitic capacitance which restricts the signal changing rate along the lines. The parasitic capacitance which is driven by a memory cell will become increasingly higher as the memory capacity is increased. According to the present invention, a differential sense amplifier is used to amplify the data signals which are read out of the memory cell. At the same time, a dummy cell is used to generate a reference potential which is to be referred to by the differential sense amplifier. In particular, a dummy cell arrangement is provided wherein each dummy cell includes at least two series-connected semiconductor elements to provide a predetermined dummy cell conductance to establish a reference value. Another aspect of the invention lies in the use of column switches between a common data line and data lines of the memory arrays for coupling only one data line at a time through the column switch to the sense amplifier. In addition, a built-in error-correcting-code circuit is provided which operates in conjunction with a selecting circuit so that memory cells delivering a predetermined set of data are spaced apart from one another by at least predetermined distances to reduce the likelihood of errors from immediately adjacent memory cells.

Capacitive pressure transducer

Abstract: The flexible membrane for sensing a differential pressure in a cylindrical sensor is made from a tube with heavy end rings that gradually taper down to form a flexible membrane such that stresses from membrane flexions are distributed throughout the end rings to prevent the stresses from being transmitted to the joints between the tube and its supporting structure thereby reducing hysteresis and creep deformation effects; temperature and stray capacitance effects are minimized by using the capacitive sensor in a tank circuit having an inductor integral to the transducer structure, the tank circuit oscillating at its resonant frequency for use in indicating the differential pressure.

X-ray tube bias supply

Abstract: 57 A power supply is switchable to apply a low kilovoltage and a relatively higher kilovoltage alternately to the anode of an x-ray tube that includes a filament and a control grid. A grid bias voltage generator uses an inverter driven in the kilohertz frequency range to feed the primary winding of a first transformer whose parasitic capacitance and inductance are used to produce a peak ac output voltage from the secondary of the first transformer at resonant frequency. The secondary output voltage is rectified and the resulting negative bias voltage is applied to the control grid synchronously with the high kilovoltage being applied to the anode so the x-ray tube current is then relatively low. A less negative or zero bias voltage is applied to the grid synchronously with the lower kilovoltage being applied to the anode so the x-ray tube current is then relatively high and substantially limited by the temperature and emissivity of the filament. A second transformer identical to the first one is used to sense the ac output voltage of the first one. A voltage-to-frequency converter switches the inverter. The resonant circuit ac output voltage sensed by the second transformer is rectified and compared with a selectable dc control signal and any resulting error signal is used to adjust the converter frequency and, hence, the inverter frequency so the bias on the x-ray tube grid voltage is proportional to the dc control signal level.

Method of and apparatus for efficient high voltage generation by resonant flyback

Abstract: This disclosure is concerned with adapting very high-voltage, low-current, high impedance power source circuits, such as CRT anode supplies and the like, to employ the efficiency over wide input voltage ranges and other advantages, including small size, of switching-mode operation through combining variable frequency (or period) output control circuitry with resonant high-voltage transformers, wherein the transformer resonant frequency is rendered comparable to the desired range of conversion frequencies; and in which resonant flyback circuit operation drives a voltage multiplier such as to accommodate the resonance caused by the stray capacitance shunting its storage inductance.

Capacitive circuit board testing system and method using a conductive pliant elastomeric reference plane

Abstract: A capacitance measuring circuit board test system (10, 10') for measuring the electrical continuity and integrity of line segments (14) on a circuit board (12) including: a test stand support (20); a conductive pliant circuit board backside reference plane (19, 29, 34) carried by the support (20); means for pressing the circuit board (12) into intimate mutually coextensive face-to-face contact with the conductive pliant material (29) defining the reference plane (19, 29, 34) with the interface therebetween being devoid of air gaps; and, a capacitance measuring device (16, 40) having sensory terminals (5, 18 and 44, 45) respectively coupled to a relatively movable test probe (11, 46) and to the backside reference plane (19, 29, 34) for measuring the capacitance of the circuit board line segments (14) between n test points and the backside reference plane (19, 29, 34). The systems disclosed include methods and apparatus suitable for use with a wide variety of circuit boards (12) including single- or double-sided circuit boards, single- or multi-layer circuit boards, and circuit boards with and/or without internal ground and/or power planes; and, with a wide variety of different types of capacitance measuring devices including, for example, three point capacitance meters (16) and four point capacitance meters (40), in the latter of which current is driven through the circuit board (12) and test system (10') from a high-potential drive terminal (41) to a low-potential drive terminal (42) associated with the meter (40) while the voltage levels at the high- and low-potential sensory terminals (44, 45) are measured with the voltage drop therebetween being indicative of line segment capacitance.

Hierarchical Circuit Extraction with Detailed Parasitic Capacitance

Abstract: This paper describes a hierarchical MOS layout verification program called IV. IV extracts a circuit netlist from a MOS layout and then compares this netlist to a reference circuit netlist obtained from a schematic. The circuit extraction phase of IV is described in detail. A unique characteristic of the program is the treatment of parasitic capacitance. IV is currently being used in a production environment to extract circuits in a variety of NMOS and CMOS processes.

MOS Analog switch driven by complementary, minimally skewed clock signals

Abstract: An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.

An analytical model for the gate capacitance of small-geometry MOS structures

Abstract: An analytical formulation of the gate capacitance of MOS structures which takes into consideration the effects of electrode thickness and lateral gate dimensions is presented. Results are presented in normalized form covering a wide range of typical device dimensions.

Analysis of the channel inversion layer capacitance in the very thin-gate IGFET

Abstract: As the gate insulator thickness approaches the channel thickness, the gate capacitance is speculated to be smaller than its gate insulator capacitance. The gate capacitance of the thin-gate IGFET is calculated using Maxwell-Boltzmann and Fermi-Dirac statistics and is experimentally measured. The results show that the gate capacitance approaches the gate insulator capacitance regardless of the gate thickness within the practical range ( T_{ox} > 50 A). To explain why the channel thickness is not reflected in the measured gate capacitance, the channel inversion layer capacitance is analyzed numerically. Based on that, its effects on the gate capacitance are discussed quantitatively and an equivalent circuit is proposed.

Switched capacitor circuit with high power supply projection ratio

Abstract: In a switched capacitor circuit, in order to eliminate leakage of a power supply noise component to a signal line through an input capacitance of an operation amplifier, (1) an operating current of at least a first, differential stage among stages of the operational amplifier is regulated by a current regulation bias circuit, and (2) a power supply noise component having the same phase as that of an input signal is applied to the gate of a transistor of a gain stage, thereby stabilizing the operating point. In order to eliminate leakage of the power supply noise component to the signal line through a parasitic capacitance of an analog switch, (3) a dummy switch is used to detect a signal corresponding to the leakage component of the power supply noise component to the signal line, and an inverted signal having the opposite phase to that of the signal corresponding to the leakage component is applied to a substrate of the analog switch, thereby cancelling the actual leakage component.

Capacitance of Open-Ended Dielectric-Filled Coaxial Lines-Experimental Results

Abstract: Capacitance of open-ended coaxial lines is determined experimentally using a resonant technique. An empirical expression for the capacitance versus frequency, which enables the open circuit to be used as a calibration standard for microwave network analyzers, is proposed and verified.

Oxide walled emitter

Abstract: A semiconductor integrated circuit device in which the side surfaces of an emitter of an oxide isolated bipolar transistor are surrounded with insulating compounds or regions so that the capacitance between the emitter and base is lowered and a base is formed by the self-alignment so that the influence of an active base between an external base and the emitter can be made negligible. Thus the base resistance and parasitic capacitance are lowered.

An RC Discharge Digital Capacitance Meter

Abstract: A simple digital capacitance meter which utilizes the RC discharge is proposed and the wide range capability from 0.1 pF to 10 mF and the excellent linearity to ± (0.02 percent of reading + 1 digit) are shown. The RC discharge capacitance meter provides the capacitance to be measured at a frequency which is reciprocal to the product of the discharge resistance and the measured capacitance. Therefore, the meter can be used to test the frequency dependence of the capacitor even though the test signal is a dc voltage. The proposed RC Discharge Capacitance Meter can also be used in applications such as the measurement of the deviation from the preset value, or the torellance check of capacitance to make the GO or NO-GO decision by adding a few logic gates.

Symbolic Parasitic Extractor for Circuit Simulation (SPECS)

Abstract: This paper describes the design, development and implementation of the program SPECS. The purpose of SPECS is to automatically extract from a Rockwell microelectronic symbolic matrix description a netlist for circuit simulation. This program differs from others in that it uses a symbol layout matrix as an input, calculates both interelectrode and intrinsic capacitance, calculates conductor resistance, produces a schematic representation of the network and has a selective TRACE, i.e., traces only the circuit or network of interest.

A switched capacitor comparator.

Abstract: A switched capacitor comparator (36) having two or more stages of differential input operational amplifiers (44, 52) utilizing sequentially switched feedback means (46, 54) and feedback capacitors (48, 56). The use of feedback capacitors (48, 56) in a sequentially switched comparator (36) provides accurate gain and stability. To further reduce offset voltage errors, a solid state transmission gate (78) having a low "on" resistance is disclosed. A transmission gate (78) having transistors (80 and 88) connected as capacitors for partially compensating parasitic capacitance effects, a P-channel device (90) and an N-channel device (84) with a switched tub or substrate is provided to compensate parasitic capacitance effects. When the transmission gate (78) is conducting, the tub or substrate of the N-channel device (84) is switched from one of its current electrodes to a reference potential such as ground. Before the transmission gate (78) is opened electrically, a settling time is provided to allow charge which is coupled from parasitic capacitance to settle.

Self-aligned submicron gate digital GaAs integrated circuits

Abstract: Digital normally-off (ENFET) GaAs integrated circuits have been fabricated using a novel self-aligned gate process that has produced high speed ring-oscillators with propagation delays as low as 25 ps and other low power circuits with power dissipation as small as 16 µW (at room temperature). The process is unique in that it permits control of parasitic FET source resistance and gate capacitance and also can achieve submicron gate lengths using conventional optical lithography.

Non-contact sensor for determining moving flat steel strip shape profile

Abstract: Method and apparatus for monitoring the flatness characteristic of a moving electrically conducting strip of material by continuously measuring the change in capacitance between the strip surface and a fixed point adjacent the surface. The capacitance is measured by means of a sensor (1) having an active plate (7) surrounded by a guard plate (2) for eliminating stray capacitance, both plates (2, 7) being impressed with a high frequency signal. Changes in capacitance associated with both plates are eliminated while changes in capacitance associated with only the active plate are converted to a voltage proportional to the inverse of the spacing between the active plate and the strip surface. A plurality of the sensors (1) may be spaced across the width of the plate (7) for providing a profile of the strip flatness characteristics. The sensor finds particular application for monitoring and characterizing bottom buckles in steel strip following high temperature annealing.

Charge redistribution mu-law PCM decoder

Abstract: An integratable PCM decoder requiring a total capacitance of only 32 times the normalized capacitance Co of the smallest capacitor thereof. The decoder comprises a source of positive and negative reference voltages, a differential input operational amplifier having its non-inverting input connected to ground, a storage capacitor CO=16Co connected as a feedback capacitor between the inverting input and the output terminals of the amplifier so that they operate as a voltage source, binary weighted capacitors C1=Co, C2=Co, C3=4Co and C4=8Co, and a second unit weighted capacitor C5=Co. In a mu-law decoder, switch means alternately connect one and other sides of ones of C1-C5 (1) between ground and either a±reference voltage or ground, in accordance with the characterizations in a PCM coded digital input word, and (2) across the storage capacitor CO for redistributing charge on the capacitors for each segment of a designated polarity. In an A-law decoder, the switch means alternately connects one and other sides of ones of C1-C5 (1) between ground and either a±reference voltage or ground, in accordance with the characterizations in a PCM coded digital input word, for sampling charge, and (2) between one side of CO and ground for transferring charge to CO for the first segment associated with a PCM word, and across the storage capacitor CO for redistributing charge on the capacitors for other segments of a designated polarity. The resultant analog signal established on CO in the eighth segment is sampled prior to resetting the charge voltage on CO to substantially zero volts and receipt of the next PCM input word. Connections of plates of integrated capacitors and electrodes of switching transistors to ground and terminals of voltages sources renders the decoder substantially insensitive to stray and parasitic capacitance effects associated with the integrated capacitors and switches.

A Simple Stray-Free Capacitance Meter by Using an Operational Amplifier

Abstract: A simple operational amplifier circuit known as a charge amplifier has an advantage of measuring capacitance independent of stray capacitance. Capacitance down to 0.03 pF could be experimentally measured with ease and the theoretical limit of measurement is discussed. Also the direct measurement of the electrostatic induction coefficients of a system of conductors by the circuit is introduced.

Switched capacitor circuit with minimized switched capacitance

Abstract: A circuit for monolithic or film stratum is adapted to have circuit capacitances integrated therein and having a minimum unit capacitance (MUC), or smallest practical capacitance that can be fabricated therein. Circuits are provided that have in one circuit arm a capacitor having a first capacity and in a second circuit arm a number N of series connected switched capacitors having a second or terminal capacity, or effective capacity between the end terminals of the second arm, that is less than the first capacity. The first capacity and second capacity form a ratio R, which is the factor by which the first capacity is greater than the second capacity. Switching is provided for each plate of each of the series connected capacitors and at the end terminals of the second arm to alternately connect the second arm into the circuit and to discharge the series connected capacitors which minimizes the effects of parasitic capacitances. Each series connected switched capacitor of the second circuit arm may have a capacity of substantially one MUC so that the terminal capacity of the second circuit arm is (1/N) MUCs and the first capacity is (R/N) MUCs. The total capacitance, or circuit capacitance, that is integrated into the stratum is (N+R/N) MUCs. N is selected to reduce or minimize the circuit capacitance and thus correspondingly reduce or minimize the integrated stratum area, reducing cost and size of the integrated stratum area for a given circuit.

Design and fabrication of depletion GaAs LSI high-speed 32-bit adder

Abstract: A GaAs LSI 32-bit adder implemented in BFL (buffered FET logic) gates has been designed and fabricated to demonstrate the feasibility of high-performance depletion GaAs LSI. Power dissipation reduction has been successfully achieved by reducing the number of level-shifting diodes to one, conforming with the FET threshold voltage (-0.5 V) and supply voltages (2 V, -1 V). Computer simulation was carried out with the interconnect parasitic capacitance included. In the IC, carry-look-ahead operation was utilized for realizing high-speed performance for 32-bit addition. The fabricated IC implementation required 420 gates, including 2100 FETs and 420 diodes, within a chip area of 4.6 mm/spl times/2.5 mm. High-speed performance was evaluated by packaging an IC chip. A maximum addition time of 2.9 ns with power dissipation of 1.2 W was obtained.

Frequency controlled excitation of a gas discharge lamp

Abstract: An electric lighting system produces light by feeding an electric tension of high frequency generated in an oscillator (21) having a transformer (24) connected to electrodes of a gas discharge lamp (20). Thereby the gas in this lamp becomes ionized, emits light and exhibits plasma resonances. The frequency of the electric tension is kept on a resonance frequency of the ionized gas by using the operating gas discharge lamp and the secondary winding (27) of the transformer as a resonant tank circuit which determines the frequency of the oscillation. The oscillator operates at either a higher or lower frequency than the plasma resonance before the lamp starts. This higher or lower frequency is determined either by the saturation of the core (K) or by the inductance and stray capacitance of the primary winding (25) of the transformer. The transformer core has an air gap calculated so that the oscillator frequency may shift in the ratio of 1:4. The oscillator frequency is between 10 KHz and 1 MHz.

Effects of collector epitaxial layer on the switching speed of high-performance bipolar transistors

Abstract: The importance of the epitaxial layer in designing the scaled-down high-performance bipolar transistors is well accepted, but its effect on the performance of the conventional switching transistors for logic application is not quite observable, because it is usually overwhelmed by the large parasitics of these devices. For self-aligned transistors having very small parasitics, its effect becomes so significant that it is observable in the power-delay characteristics of the switching circuits. We built self-aligned transistors on epitaxial layers of different thicknesses. The measured switching speed of transistors with thicker epitaxial-collector layers is faster at lower currents due to the lower collector capacitance; but it is slower at higher currents due to the base stretching. The present experimental results provide direct confirmation of the design theory [1].

SiGMOS—A silicon gigabit/s NMOS technology

Abstract: A n o v e l f i n e l i n e s i l i c o n NMOS technology, SiGMOS, has been deve loped to ach ieve as h i g h a s p o s s i b l e c i r c u i t s p e e d s . I n v e r t e r p r o p a g a t i o n d e l a y s p e r s t a t e of 78, 64 , 43 and 33 psec have been ob ta ined fo r dev ices wi th an e f f ec t ive wid th o f 5 .5 um and e f f e c t i v e c h a n n e l l e n g t h s o f 1 .25, 1 .00 , 0.75 and 0 . 5 um, r e s p e c t i v e l y . T h e s e a r e t h e s m a l l e s t d e l a y s p e r e f f e c t i v e c h a n n e l l e n g t h e v e r r e p o r t e d f o r a s i l i c o n MOS t echno logy , and t hey r ep resen t a f a c t o r o f two improvement compared t o mos t p rev ious r e su l t s .

Very Wide-Band Silicon Bipolar Monolithic Amplifiers

Abstract: We have developed very wide-band monolithic amplifiers, using an advanced silicon bipolar process called SST-2 which made it possible to lower base resistance and parasitic capacitance. Analog ICs, such as AGC and post amplifiers, for repeater circuits of a high speed optical fiber transmission system were fabricated, and the following excellent characteristics were obtained. (1) The gain and 3 dB down bandwidth of the post amplifier are 15 dB and 1.4 GHz, respectively. (2) The maximum gain, 3 dB down bandwidth and dynamic range of the AGC amplifier are 28 dB, 630 MHz and 30 dB, respectively.

Monolithic integrated circuit device including AC negative feedback type high frequency amplifier circuit

Abstract: A monolithic integrated circuit device is formed on a substrate and made up of an AC negative feedback circuit for a high frequency amplifier circuit The AC negative feedback circuit includes a semiconductor impedance element and connected to an external terminal on the substrate, and variable control means for adjusting an amount of the AC feedback of the high frequency amplifier circuit As the semiconductor impedance element is used the junction capacitance of a diode under negative bias, diffusion capacitance between the base and emitter electrodes or between the base and collector electrodes of a transistor or a differentiated resistance of a diode