Showing papers on "Parasitic capacitance published in 1984"

The effect of high fields on MOS device and circuit performance

Abstract: A simple analytical model for the MOS device characteristics including the effect of high vertical and horizontal fields on channel carrier velocity is presented. Analytical expressions for the drain current, saturation drain voltage, and transconductance are developed. These expressions are used to examine the effect of scaling the channel length, the gate dielectric thickness, and the bias voltage on device characteristics. Experimental results from various geometry MOS devices are used to verify the trends predicted by the model. Using the physical understanding provided by the model, we examine the effect of device geometry scaling on circuit performance. We suggest that for gate capacitance-limited circuits one should reduce the channel length, and for parasitic capacitance-limited circuits one should reduce the gate dielectric thickness to improve circuit performance.

Distributed capacitance LC resonant circuit

Abstract: An electronic article surveillance system and a marker for use therein, which marker comprises a tuned resonant circuit including inductive and capacitive components formed of a laminate of a dielectric and conductive-multi-turn spirals on opposing surfaces of the dielectric, wherein the capacitive component is formed as a result of distributed capacitance between the opposed spirals, and wherein the circuit thereby resonates at at least two predetermined frequencies which are subsequently received to create an output signal.

Electrical and Dielectric Properties of Wet Bone as a Function of Frequency

Abstract: The electrical and dielectric properties of wet, bovine, compact bone were determined in three orthogonal planes, using a differential technique, for a frequency range of 1 kHz-l MHz. For axial specimens, at 10 kHz, the specific resistance, specific capacitance, and specific impedance were 16.6 k?/cm, 60.9 pF. cm-1 and 16.59/?3.65°k?·cm, respectively. Similarly, the dielectric properties, namely the relative dielectric constant, relative dielectric loss factor and dielectric dissipation factor were 688, 10.8 ×103, and 15.7, respectively. The electrical properties were found to be highly dependent on the frequency and the moisture content of bone. The bone was also found to be highly anisotropic in its electrical behavior, the impedance being lowest in the axial direction. It is shown that the differential method provides an accurate means of measuring the electrical properties of bone, avoiding stray capacitance errors.

EXCL: A Circuit Extractor for IC Designs

Abstract: This paper describes EXCL, an automated circuit extraction program that transforms an IC layout into a circuit representation suitable for detailed circuit simulation. The program has built-in, general extraction algorithms capable of accurate computations of interconnection resistance, internodal capacitance, ground capacitance, and transistor sizes. However, where possible, the general algorithms are replaced with simple techniques, thereby improving execution speed. A basic component of the extractor is a procedure that decomposes regions into domains appropriate for specialized or simple algorithms. The paper describes the decomposition algorithm, the extraction algorithms and discusses how they connect with the rest of EXCL.

Capacitive coupling type data transmission circuit for portable electronic apparatus

Abstract: A capacitive type coupling data transmission system for portable electronic apparatus is comprised of an input circuit, a capacitance changing circuit, a transmitting circuit capacitively coupled to, a receiving circuit, and a detecting circuit for detecting any change in the capacitance changing circuit. A data signal to be transmitted is inputted into the input circuit. Based on the value of an inputted binary digital data signal, the capacitance of the capacitance changing circuit is changed. The capacitance change is capacitively transmitted from the transmitting circuit to the receiving circuit and detected thereat. The detecting circuit may be an oscillator circuit, a an RC differentiating circuit, or an RC integrating circuit.

Bipolar transistor-field effect transistor composite circuit

Abstract: A bipolar transistor-complementary field effect transistor composite circuit is provided which includes a pair of first and second bipolar transistors each having a collector of a first conductivity type, a base of a second conductivity type and an emitter of a first conductivity type. Collector-emitter current paths of the bipolar transistors are connected in series to each other between first and second potentials, with a connection node providing an output of the composite circuit. Field effect transistors are respectively coupled between the bases and collectors of the bipolar transistors for controlling the on-off states of the bipolar transistors in opposite relationship to one another in response to an input signal provided to the composite circuit. Also, discharge arrangements are provided for the bases of the first and second bipolar transistors to discharge parasitic capacitance in the bases of the first and second bipolar transistors when they are turned off.

Capacitive pressure transducer signal conditioning circuit

Abstract: Signal conditioning circuitry for a three plate capacitive pressure transducer eliminates the effects of parasitic capacitance in the transducer's output, to provide a true indication of sensed pressure magnitude as an electrical signal equivalent of the instantaneous value of only the pressure responsive capacitance of the transducer.

Complementary MOS circuit having decreased parasitic capacitance

Abstract: The substrate voltages V 1 and V 2 of NMOS and PMOS transistors, respectively, which constitute a CMOS circuit and the source voltages V 3 and V 4 of these transistors have the following relationship: V.sub.1

Capacitive gauging method and apparatus

Abstract: Method and apparatus for deriving a correction factor used in calculating corrected liquid (e.g., fuel) quantity of a tank having a probe capacitance which varies in accordance with the quantity of liquid contained within the tank. The correction factor reduces sensing diode voltage drop errors and stray capacitance errors (affecting the capacitance of the probe) through use of a switchable high/low amplitude Lo-Z oscillator. All oscillator outputs are "low" amplitude relative to the output amplitudes of conventional devices. Signal processing is effected by inputting raw data (both reference and probe-sensed signals) to an analog-to-digital sampling circuit, which raw data are used for deriving the correction factor. The correction factor is then applied to the raw data to determine a corrected liquid quantity indication. Recalibration of the correction factor periodically permits automatic adaption to changing error magnitudes (i.e., changes in the deleterious effects of diode-voltage drop and/or stray capacitance). Additionally, the relative "health" of the component elements of the tank unit is monitored by tracking changes occurring during recalibration of the correction factor. Establishment of a correction factor outside a predetermined range might indicate faulty probe components or other such difficulties. Numerous practical advantages and economies are obtained by the method and apparatus presently disclosed because of the enabled use of an oscillator with a relatively low voltage output (e.g., under 10 volts peak).

On the frequency limitations of SC filters

Abstract: Representative closed-form expressions are derived for a stray-insensitive integrator which describe the combined influence of the amplifier finite gain and finite bandwidth and of the nonzero on-resistance of the switches. In this way, a technology-dependent upper frequency limit is obtained for the application of typical stray-insensitive switched-capacitor circuits. The deteriorating effect of switch-on resistance and stray capacitance is also derived for integrator circuits comprising unity-gain amplifiers. However, the results obtained shown that they are too much affected by the parasitic capacitances to be a serious alternative for monolithic high precision filters.

Switched-capacitor delay circuit that is insensitive to capacitor mismatch and stray capacitance

Abstract: A new switched-capacitor delay circuit which uses only a single amplifier and is insensitive to capacitor mismatch and stray capacitance is proposed. The insensitivity to capacitor mismatch permits the use of very small-valued capacitors so that the chip area can be reduced by device scaling as the feature sizes are reduced due to improvements in technology. Tapped analogue delay lines using such delay elements would be ideal for realising programmable and adaptive filters and equalisers in analogue LSI.

Equalized capacitance wiring method for LSI circuits

Abstract: A method for equalizing the capacitances of a plurality of circuits in order to compensate for different signal transmission delay times within an LSI circuit. The wiring capacitance of the individual circuits are measured and the maximum capacitance value in a circuit group is determined. An equalizing capacitance pattern, which has a capacitance corresponding to the difference between the maximum capacitance value and the capacitance value of an individual circuit, is applied to each individual circuit.

Floating input comparator with precharging of input parasitic capacitors

Abstract: The present invention relates to a floating input comparator capable of mitigating the effects of parasitic capacitance present at the input stage of the comparator. In particular, the present invention functions to substantially reduce the effects of parasitic capacitive voltage division present at the nodes interrogated during each detection cycle. In accordance with the present invention, precharging devices (40, 42, 44) are coupled between a predetermined reference potential (VDD) and the affected nodes (D, E, C) to precharge the nodes to the full reference potential prior to each detection cycle, thereby eliminating the effects of a changing, unknown parasitic capacitance at these nodes by replacing an unknown parasitic potential with the known reference potential.

A Switched-Capacitor Digital Capacitance Bridge

Abstract: A switched-capacitor bridge has been developed for capacitance measurements. It consists of four arms connected between the low-impedance output and virtual ground nodes of an op-amp, and hence is insensitive to parasitic capacitances. The capacitance to be measured is first given a proportional charge. This charge is then compared successively with charges quantized by means of a programmable binary-weighted capacitor array, until a balance is reached. This digital balance operation makes it possible to accomodate an automatic calibration scheme, which affords, in conjunction with the parasitic-insensitive configuration, an accurate measurement. Error analysis has shown that a 10-bit quantization accuracy and a relative error as small as 0.1 percent are attainable when the bridge is fabricated in LSI circuit form using present MOS technologies. A prototype bridge built using discrete components has confirmed the principles of operation. Examples of measurement are also given.

Read-only memory

Abstract: A read-only memory has word lines (9) and ground tines (10) extending linearly and parallel to each other above a semiconductor substrate, and data lines (11) extending perpendicularly to the word lines (9) The data lines are connected via connection (24) to impurity regions 14 in the substrate, which regions (14) are drains of MOS transistors being the data storage elements of the memory The sources of the MOS transistors are formed by impurity regions (141) connected via connections 23 to the ground lines (10), and the word lines (9) extend over the gates of the transistors This structure enables a very compact memory to be achieved, thereby permitting a high integration density, with a low parasitic capacitance and parasitic resistance In one embodiment, the word and ground lines (9, 10) are formed by a common metal layer, whilst in a second embodiment the ground and data lines are formed by a common metal layer

Bi-CMOS Circuits for High Performance VLSI

Abstract: A circuit technique combining CMOS and bipolar circuits to achieve high performance at low power has been demonstrated. The circuits have been fabricated and measurement results showed the performance is substantially better than CMOS. Applications of this technique to gate arrays and standard cell based VLSI are discussed.

Circuit for high impedance broad band probe

Abstract: A zero capacitance measurement probe to be used to make electrical measurements at a broad range of frequencies without having the probe itself affect the measured values. The probe reduces internal capacitances in the solid state active elements or creates a negative impedance to counteract capacitance external capacitance. Elimination of capacitance is accomplished by adjusting gains and current flow within active elements and by insulating the elements from ground by an additional substrate and metalized layer.

A capacitance coupled bit line cell for Mb level DRAMs

Abstract: CIRCUIT TECHNIQUES developed for a stacked capacitor 256Kb NMOS DRAM test model to achieve the best use of a small cell ( 3 8 . 2 5 ~ 2 ) used as a storage element will be reported. In the development of next generation DRAMs, a certain storage capacitance value (approximately 50fF) must be assembled in the small cell area with minimal capture rate of minority carriers in the substrate. Conventional double polysilicon cells are becoming obsolete for these requirements. Among several improved cell structures, the stacked capacitor cell’ affords larger storage capacitance by extending the storage region onto the transfer gate. The use of capacitive-coupled bit lines (CCB) in triple polysilicon cell structures are similar, but have an approximately 1.5 times larger storage area, because the total cell area is utilized for the capacitor. Figure 1 shows a plane and cross sectional view of the cell. A large storage area was created by reciprocally connecting the transfer-gate and the capacitor. This has eliminated the space for a contact hole between bit line to cell. The cell output voltage of CCB and standard metal bit line structures were compared: Figure 2 shows the calculated output voltage as a function of cell size. Lateral dimensions including storage capacitors were assumed to vary with cell size, while the spacing between capacitors and the metal bit line width were kept constant because the minimum line width and the spacing were assumed. Vertical dimensions were also kept constant. A two-dimensional numerical analysis method was used for capacitance evaluation, and the effects of capacitance between adjacent bit lines were taken into account. Since the bit line width of CCB structures varies with cell size, the parasitic capacitance is comparably large for cell sizes over 4 0 m 2 and the output voltage is lower than that for metal bit line structure. But if the memory cells are very small, the situation is reversed; the capacitance of metal bit lines does not reduce much with cell size due to fringe Capacitance components and the emergence of capacitance between bit lines, while the capacitor area rapidly decreases. For the same output voltages, a CCB cell with larger storage capacitance is more resistive to soft errors and superior performance is expected from very small cells. The cell’s operational biases are slightly different from conventional cells. In write operations, bit lines are set at the V,, or Vss level according to the data being written. The voltage source lines provide a Vcc level to each storage node __

Light detecting circuit

Abstract: A light detecting circuit in which noise superposed on a bias voltage of a photodiode is substantially canceled without the aid of a filter circuit employing an inductor. The photodiode is connected between a bias voltage terminal and an inverting terminal of a main amplifier, the latter being implemented with a differential amplifier or a comparator. A capacitance device is connected between the same bias voltage terminal and the other (noninverting) input terminal of the main amplifier. The capacitance device may be either a physical capacitor or a second photodiode which, in either case, should have a capacitance equal to the parasitic capacitance of the first photodiode.

Method of fabrication of a low capacitance self-aligned semiconductor electrode structure

Abstract: Semiconductor electrode structure with low parasitic capacitance and method for forming low capacitance first and second electrodes in a semiconductor device, such as a static induction transistor, while avoiding the requirement for precision mask alignment and mask to mask registration. During formation of electrode contacts, the first electrodes are protected by silicon nitride and a low resistivity silicon layer is grown over the semiconductor wafer, forming epitaxial regions over the second electrodes of a polycrystalline region over protected portions of the wafer. The silicon layer is selectively etched by a mixture which removes the polycrystalline region but does not appreciably affect the epitaxial regions. Second electrode metallic contacts are made in enlarged regions of the second electrodes where mask alignment is not critical. The reduction in contact window overlap by metallic contacts reduces parasitic capacitance.

An analytical model for intrinsic capacitances of short-channel MOSFETs

Abstract: Precision characterization of intrinsic gate capacitances of small-geometry MOSFETs is needed for the design of analog, as well as some digital circuits, such as memories. A new and simple measurement technique for intrinsic MOSFET capacitances which does not require any on-chip circuitry, is applied to short channel devices. The short-channel transistor capacitance characteristics are found to deviate from those of the long-channel transistors in many aspects. An analytical model to explain the measurement results, especially the short-channel effects and above-threshold characteristics, is described. This new mode includes the mobility degradation effect, velocity saturation effect, bias-dependent fringing-field effect, as well as source/drain series resistance effect. Good agreement between the measured and simulated results is found.

Storage element circuit

Abstract: PURPOSE:To always attain high speed operation and low power consumption operation without causing a difference in operating speed by providing a circuit setting a precharge voltage to an intermediate value at the high speed to cut off a DC path between two power supplies of a memory circuit. CONSTITUTION:When transistors (TRs) TR1, TR4 are turned on by a precharge signal, the level reaches a threshold value LLT2 of an inverter 5 higher than a threshold value VLT1 of an inverter 4 of a detection circuit 10 and until a TR3 is turned off, precharging is applied, and the common data line of a row selecting circuit 3 is precharged rapidly to an intermediate voltage. The precharge is started almost at the same time as the selection of column by the circuit 3 and finished before a row selection, the TRs TR2, TR4, TR10 shut off the DC path between the two power supplies of a memory element 2 of a memory matrix 1, and low power consumption requiring only the charging current to the parasitic capacitance of the circuit is obtained. Moreover, the initial state is ensured at all times by a discharge TR of the circuit 3 to attain high speed and low power consumption not causing no difference in the operating speed.

A method for extracting SPICE2 junction capacitance parameters from measured data

Abstract: This paper describes a method for extracting SPICE2 junction capacitance parameters from measured data. The method is efficient and accurate, and is easily integrated into an automatic test and data analysis system.

A high reliability high sensitivity lightwave receiver for the SL undersea lightwave system

Abstract: Undersea lightwave systems need receivers with the utmost in both reliability and sensitivity. Our design has evolved from the type which we provided for an earlier deep-sea trial. The primary features of our present receiver are an InGaAs planar p-i-n photodiode with passivation and antireflection coating and a Si bipolar integrated circuit, both encapsulated in a special chip carrier. Both the photodiode and the amplifier are placed in the same carrier so that a direct chip-to-chip wire bond can minimize stray capacitance, which helps to maximize sensitivity. The back-illuminated structure of the photodiode allows the InP substrate to serve as a window in the hermetically sealed carrier. Since both active devices are in a separate package from the passive components, they can undergo the high temperature bake-out and hermetic seal followed by the high temperature high bias purge necessary to assure the reliability of the semiconductors. This optical chip carrier is then mounted inside another hermetic package which contains the passive components, including the optical fiber pigtail, which must undergo bake-out and seal at more moderate temperatures. Within the constraints of reliability, bandwidth, and dynamic range, the physical structure of the integrated circuit and its bias conditions have been chosen to maximize sensitivity. The design of the circuit enables us to select those devices from a production lot which will achieve the highest sensitivity in a completed receiver. This receiver is used in systems operating with NRZ data from 140 to 440 Mbit/s. At 1.3 μm and 296 Mbit/s the mean sensitivity achieved was an average optical power \bar{P} = -35.6 dBm for a 10-9bit error rate (BER), with a best value of -36.3 dBm. This receiver is physically robust, being able to withstand stresses well in excess of those encountered in actual use. Preliminary aging data indicate that a long-term failure rate of less than 2.5 in 109device hours can be achieved.

Capacitance type converter

Abstract: PURPOSE:To remove the influence of stray capacitance by connecting a variable capacitor corresponding to a capacitor to be measured and a reference capacitor to the 1st rectifying circuit, controlling the oscillators of both the capacitors by the output of the 1st rectifier circuit, and obtaining an output from the 2nd rectifier circuit for the reference capacitor. CONSTITUTION:Respective fixed electrodes 16, 17 of variable and reference capacitors 11, 12 in a detecting part 10 are connected to the inverted input terminals of operational amplifiers A1, A2 of detecting circuits 51, 52 constituting the 1st and 2nd rectifier circuits respectively and the positive input terminals are connected to a common electrode 15 in the detecting circuit 10 through a reference point oscillator 20. On the other hand, the outputs of the amplifiers A1, A2 are fed back to respective inverted input terminals through feedback circuits consisting of resistors R3, R4, etc. respectively. A DC voltage from the amplifier A1 and a negative reference voltage are inputted to the inverted input terminal of an operational amplifier A3, the oscillator 20 is controlled by the output of the amplifier A3 and an output EOUT related to a capacitance value of the capacitor 11 corresponding to the capacitance to be measured is extracted from the circuit 52.

Ultra high speed photodetectors

Abstract: In this paper we will discuss the design and characterization of an ultra-high speed GaAs Schottky barrier photodiode whose -3 dB power bandwidth is 100 GHz or equivalently in the time domain a full width half maximum (FWHM) of 5.4 picoseconds. The 100 GHz bandwidth is attained at an operating reverse bias of only 5 volts. The device consists essentially of a semitransparent Pt-film forming the Schottky barrier on n GaAs an n+ GaAs epitaxial layers grown on semi-insulating CaAs substrate. Ohmic contact is formed on the top surface completing the device. Details of the fabrication process will be presented. Parasitic capacitance of such a structure is less than 15 femtofarads and the junction capacitance is 20 femtofarads for a photosensitive area of 25 square microns. Beam-leads bare been added to the structure to minimize inductances. It will be shown that this structure is particularly adapted for monolithic integration with a field effect transistor (9,39). High speed photodetectors, mostly infrared to far infrared, have being in existence for many years and these will he briefly mentioned and referenced. To limit the scope of this presentation, only photon-effect devices (devices whose operation depends on the creation of an electron/hole in the semiconducting material) in the photoconductive and photovoltaic modes will be considered. The characterization of the speed of response of these ultra-fast photodetectors requires the development of a novel measuring technique known as the electro-optic sampling method

Filter circuit tunable to microwave frequency, and implementation of the same

Abstract: The specification relates to the circuitry of a filter tunable to microwave frequencies. The circuitry comprises two successive transverse branches of the same type, which are at each end connected to ground and each of which includes, connected in series, a fixed inductance (L1;L2), an adjustable inductance (L4; L5), a capacitance diode (D1;D2), and a high frequency by-pass, in which case the capacitance diode (D1; D2) is controlled by means of a DC signal and there is a coupling element, e.g. a series inductance (L3) between the input point and output point of the filter. it is possible to cover the frequency range 950...1750 MHz by using economical Si capacitance diodes, by replacing the capacitor which serves in prior filters as a high-frequeny by-pass with a series resonance circuit, which preferably comprises a capacitance diode (D3; D4) and an adjustable inductance (L6; L7). The implementation of the circuitry by using a two-sided circuit card is also described.