Showing papers on "Parasitic capacitance published in 1989"

Dc/dc converter switching at zero voltage

Abstract: A two switch, DC/DC converter provides sufficient inductive energy storage at the termination of the "on" period of each switch to alter the charge on the intrinsic and stray capacitance of the combination of switches producing zero voltage across the alternate switch prior to its turn on. A short dead-band between the turn on pulses provided by the control circuit allows time for this transition. Thus the energy stored in the capacitance of the switches is returned to the source and load rather than being dissipated in the switching devices. This greatly improves the efficiency of the converter particularly when operating at high frequency. The unique topology of the converter provides other new and useful characteristics in addition to zero voltage switching capability such as operation as constant frequency with pulse-width-modulation for regulation, quasi-square wave output current, and the ability to integrate the magnetic elements with or without coupling.

SRAM with local interconnect

Abstract: An SRAM using TiN local interconnects. This permits the moat parasitic capacitance to be reduced, and also avoids use of metal jumpers, resulting in increased density.

Charge balanced feedback transmitter

Abstract: A charge balanced feedback type transmitter (10) generates charge packets representative of a sensed parameter. Improved performance is achieved by the addition of resistance (R1), (R2) connected between a charge packet generating reactance (C1), (C2), (CL1), (CL2) and an integrator (30) to reduce the effects of noise caused by switching transients and by ground noise which is coupled to the charge packet generating circuitry (12) by stray capacitance. The charge packets are integrated by the integrator (30), and the integrator output is supplied from a selective basis to the input of a comparator (32). The output of the comparator (32) is used to control the application of balance. The input of the comparator (32) is selectively connected to the output of the integrator (30), to a first supply voltage, or to a second supply voltage to ensure a stable output of the comparator (32) at a critical time when charge is being supplied to the integrator (30).

High frequency switched mode resonant commutation power supply

Abstract: A forward switched mode converter power supply of a resettable type, in which leakage inductance in the input circuit, the parallel inductance of the transformer and the parasitic capacitance of the switching means provides a resonant circuit for recirculating commutation energy, so that the voltage across the switching means is reduced essentially to zero at the beginning of each switching cycle to prevent loss of the commutation energy

Semiconductor memory device

Abstract: PURPOSE:To dispense with an oxide film to isolate memory cells, by arranging, in a substrate, a first conductivity type region whose periphery is insulated with an insulating plate, and arranging, in said region, a MOS electrode and a conducting region serving in combination as a bit line or a capacitance electrode. CONSTITUTION:On a P-type semiconductor substrate, is formed an insulating plate 2, by which almost all part of side surface and bottom of the P-type region are electrically insulated. In this P-type region 3, the following are formed; an N type region 5 serving as a capacitance electrode and one side electrode of a MOS type transistor, and an N type region 4 serving as a bit line and the other side electrode of the MOS transistor. Thereon a capacitance electrode 6, an insulating film 7, and a gate electrode 8 are formed. Further thereon are formed a word line 10 connected to the gate electrode 8 via an insulating film 9, and a protecting film 11. Thereby unnecessitating a field oxide film to separate memory cells. Further a contact region between the bit line and MOS transistor electrodes is unnecessitated, and parasitic capacitance can be reduced.

Driven guard probe card

Abstract: A semiconductor probe card with electrically separate driven guards for each probe. The probe card has electrically separate fingers surrounding each signal point contact which act as driven guards for reducing leakage problems and stray capacitance on the card. Microstrip ceramic blade probes are attached to the card at each finger. The microstrip ceramic blade probes have a conducting trace on one side which provides connection between the circuit being tested and the testing equipment. The other side and the mounting surface of the probe have ground planes which act as driven guards to further reduce leakage and stray capacitance. When connected to the testing equipment, the testing equipment drives the fingers and the ground planes on the probe to the same potential as the signal from the circuit.

An Efficient Finite Element Method for Submicron IC Capacitance Extraction

Abstract: We present an accurate and efficient method for extraction of parasitic capacitances in submicron integrated circuits. The method uses a 3-D finite element model in which the conductor charges are approximated by a piece-wise linear function on a web of edges located on the surface of the conductors. This yields a system of Green's function integral equations that is solved by a novel approximate matrix inversion technique that only utilizes the entries corresponding to pairs of finite elements that are physically close to each other. With N representing the size of the layout, this results in time and space complexities of O(N) and O(PIN) respectively. The method has been implemented in an efficient layout to circuit extractor and experimental results are presented.

Linear capacitance displacement transducer

Abstract: A linear capacitance displacement transducer for measuring absolute displacement is formed from a coaxial variable capacitor and a precision capacitance measuring electronic circuit. The plates of the coaxial capacitor are attached to the members of an assembly whose displacement relative to one another is to be determined. Linear displacement of the members causes a linear displacement between the capacitor plates which is reflected in a linear capacitance change. A capacitor controlled oscillator utilizes the coaxial variable capacitor at its input. The capacitor controlled oscillator whose period of oscillation is been determined by the capacitance and locked in phase with changes of capacitance is utilized as a precision measure of capacitance. The period of the square wave output of the oscillator is a linear function of the capacitance of the variable capacitor at any time. The transducer may be adapted to determine the absolute position of a piston rod in a hydraulic cylinder.

Ultrahigh-speed 1.55 mu m lambda /4-shifted DFB PIQ-BH lasers with bandwidth of 17 GHz

Abstract: Ultrahigh-speed 1.55 µm λ/4-shifted DFB PIQ-BH lasers with best-ever 17 GHz bandwidth as a DFB laser have been developed. This large bandwidth is attained by reducing the parasitic capacitance with a low doped p-InP burying layer and a PIQ (Hitachi Chemicals polyimide) layer, and by enhancing the relaxation oscillation frequency by optimisation of the waveguide structures.

Non-resonance AC power source apparatus

Abstract: An AC power source apparatus to be used in an AC corona generator necessary for a de-electrifica­tion/separation process, which is one of electrographic image forming processes, or in a case where a low fre­quency AC power source is required, has a construction such that a high-frequency pulse, whose time ratio is modulated trapezoidally with time, is applied to switching elements (2, 3) connected in inverse-series across a primary winding of a transformer (1), an inductance element (5) having a regenerative diode (6) and a reset winding is inserted between an intermediate tap of the primary winding of the transformer and a DC power supply input terminal (12), and an LC filter is formed by stray capacitance of a secondary winding of the transformer, whereby a desired output waveform can be produced with a simple circuit construction.

High-speed InGaAlAs/InAlAs multiple quantum well optical modulators with bandwidths in excess of 20 GHz at 1.55 mu m

Abstract: The modulator has a large on/off ratio, a low driving voltage (4 V), and operates in the 1.55- mu m wavelength region. Small device capacitance (0.2 pF) has been obtained by using spin-coated polyimides under the bonding pads, and small stray capacitance (0.07 pF) and bonding wide inductance (0.3 nH) have been realized. The modulator requires the lowest power yet reported for a high-frequency-operation external modulator. >

Interfacing control circuit with active circuit charge or discharge

Abstract: An interface control circuit comprising a buffer, an inverter, an OR gate and delay means. The interface control circuit can be utilized in digital systems for communication handshaking such that a buffer output current will actively flow through line stray capacitance thereby greatly reducing the rise time from a LOW state to a HIGH state, or charges in the line stray capacitance will actively discharge through the buffer means if negative logic mode is used thereby enabling a great reduction in fall time, therefore a much faster and efficient digital system can be obtained through the use of the invention.

A.C. capacitive gauging system

Abstract: A compensated capacitive probe system in which the probe and a guard ring are placed in the feedback path of an operational amplifier. An input signal is applied to the operational amplifier in combination with a portion of the guard signal. The resulting configuration compensates for stray capacitance at a measuring electrode of the probe and for the fact that the operational amplifier is other than mathematically ideal.

Analysis and design of a-Si TFT/LCD panels with a pixel model

Abstract: The design of a-Si thin-film-transistor/liquid-crystal-display (TFT/LCD) panels using a pixel model which consists of an equivalent electrical circuit and includes parasitic capacitance and the actual structure of deposited layers is discussed. The model's validity is first confirmed by comparing calculations with experimental results on a-Si TFT switching characteristics and TFT/LCD electrooptical characteristics. The gradual-channel approximation of an MOS transistor is applied to the static I-V characteristic of a-Si TFTs. This approximation is successfully used to obtain an analytical expression for pixel electrode voltage during the TFT turn-on time. The calculated dependence of the LCD panel transmittance on signal voltage is shown to reproduce the experimental results. On the basis of the analysis, a TFT-addressed 5-in.-diagonal liquid-crystal color TV has been developed which exhibits excellent display quality. >

Impact of stray capacitance on HVDC harmonics

Abstract: Stray capacitances inherent to HVDC converters are shown to cause all triplen harmonics to appear on the DC side. In particular, odd-triplen harmonics are produced which in a bipolar DC system will cause ground-mode simulation of the DC transmission line. The levels predicted by simulation can be large enough to cause significant telephone interference if the DC filtering, including both pole and neutral buses, is not designed to accommodate these harmonics. Field experience provides qualitative support for this theory. >

High efficiency gate driver circuit for a high frequency converter

Abstract: A high efficiency gate driver circuit for driving a power switching device of a high frequency power converter utilizes a series resonant circuit to reduce or substantially eliminate turn-on switching losses. The resonant circuit comprises the input capacitance of the power switching device and an inductance connected in series between the upper and lower switching devices of a half-bridge driver circuit. During device turn-on, the input capacitance resonates up to a voltage level approximately twice that of the gate drive power supply, and turn-on is substantially lossless. The input capacitance is prevented from discharging back to the supply by a Schottky diode connected in series between the supply and the upper switching device of the half-bridge. During device turn-off, the input capacitance discharges through the lower switching device.

A Three-Pulse Model of D.c. Side Harmonic Flow in HVDC Systems

Abstract: This paper presents a new model for the analysis of d.c. side harmonic current flow in HVDC systems. In recent years field measurements of d.c. side harmonic currents and induced voltages on parallel test lines have indicated the presence of triplen order harmonics of high magnitude. Such harmonics are not predicted by a conventional analysis of d.c. harmonics. An increase in the level of characteristic 12-pulse harmonics above the calculated values has also been noted. The discrepancy between calculated and measured values of harmonic current is attributed to the omission from the classical model of the ground path formed by the various stray capacitances of the converter transformers, bushings, and buswork. The new model proposed by the authors includes this stray capacitance. As it is essential to model correctly the harmonic driving voltages between the converter terminals and the stray capacitances, each 12-pulse converter is represented in the new model as four three-pulse harmonic voltage sources connected in series, as shown in Figure 1. The paper derives the harmonic voltages for each threepulse source and justifies the representation of stray capacitances and the internal impedance of the converter. A detailed analysis is given of the flow of harmonic currents of both odd and even triplen orders, in balanced and unbalanced bipolar and monopolar operation.

Output buffer circuit having a level conversion function

Abstract: An output buffer circuit includes a prestage circuit which generates a first potential and a second potential (an intermediate voltage) based on the voltage of an input signal. The first potential is higher than the second potential. A final-stage circuit generates an output signal by controlling a current passing therethrough from a power source on the basis of the potential of the input terminal. The output signal is supplied to an ECL circuit through the output terminal. A control circuit generates a control signal during a predetermined time when a change in voltage of the input signal occurs. A bypass circuit sets the potential of the input terminal of the final-stage circuit lower than the second potential and discharging a parasitic capacitance coupled to the input terminal during the predetermined time defined by the control signal supplied from the control circuit when the prestage circuit outputs the second potential in response to a change in voltage of the input signal.

High-frequency parallel resonant converter for X-ray generator utilizing parasitic circuit constants of high voltage-transformer and -cables

Abstract: The authors describe a resonant PWM (pulse-width-modulated) inverter-linked DC-DC converter which uses the high-voltage transformer parasitic LC circuit parameters as resonant components and the high-voltage cable input capacitance as smoothing filter. Theoretical results obtained by computer-aided simulation and experimental results obtained by a test circuit including prototype transformers are illustrated and discussed from a practical point of view. The phase-shift PWM control for adjusting the DC output voltage of the resonant converter is presented. One of the advantages of this converter is minimization of circuit components; this kind of circuit topology can minimize the size and weight of power supply systems and can be applied to the filament heating circuit connected to the cathode of the X-ray tube. >

A 60-ns 16-Mbit DRAM with a minimized sensing delay caused by bit-line stray capacitance

Abstract: Discusses three new techniques that were implemented in a CMOS 60-ns 16-Mbit DRAM device (1) A two-step half-conductive-state technique was used to control the conductivity of latch transistors, thus minimizing the time delay caused by bit-line stray capacitance (2) The 'split-block row decoder' technique enabled the decoder layout within the 29- mu m cell pitch required for 16-Mbit integration density The three transistors that are required per word line were split into two and one, placed on both sides of each word line, and alternately reversed on each side of the 2-Mbit cell array (3) Additional dummy cells were added to the vacant spaces resulting from use of a twisted bit-line architecture, which reduces stray capacitance between adjacent bit lines The overhead space required for all the dummy cells and twisted bit lines was thus held at 26 percent of the entire chip area >

Inverter device including parallel resonant circuit using a total equivalent capacitance

Abstract: An inverter device is provided, which carries out a switching action in response to a drive signal (V GS1 -V GS4 ) having a single frequency. An inductance element (L) is connected in parallel with the output terminals of the device and capable of a parallel resonance with a total equivalent capacitance which is the sum of an equivalent electrostatic capacitance of the inverter device (Q1-Q4), as observed from the output terminals toward an input side, and an equivalent electrostatic capacitance of a load (LO). With this arrangement, the charge and discharge loss due to the source-drain capacitance (C OSS1 -C OSS4 ) is reduced, and the efficiency is improved.

Method and apparatus for preventing parasitic electrical discharges in magnetic disk drives

Abstract: A method and apparatus for operating a magnetic disk drive having a pole piece spaced apart from a magnetic disk surface by a predetermined distance to effectively form two plates of a parasitic capacitance capable of sustaining an undesirable electrical discharge capable of destroying data on the disk either by random discharge between the pole piece and magnetic disk or by discharge into imperfections on the disk. The invention comprises a circuit and method for applying a DC voltage to the pole piece and for simultaneously applying a DC voltage to the magnetic disk surface which is approximately equal to the DC voltage applied to the pole piece and thereby preventing the above parasitic capacitance between the pole piece and the magnetic disk surface from charging to a level sufficient to sustain any electrical discharge.

C3DSTAR: a 3D wiring capacitance calculator

Abstract: A description is given of C3DSTAR, a capacitance program for three-dimensional configurations of conductors and dielectrics, that incorporates a hybrid integral-equation solution of the capacitance problem. The hybrid method combines the use of multilayer Green's function treatment of the infinite planar dielectric interfaces with an explicit treatment of the bound charge at finite and/or irregular dielectric interfaces. The approach described differs from previous hybrid integral equation methods in that the free charge density is the primary unknown, rather than the total charge density. This allows early elimination of numerically induced asymmetry in the capacitance matrix and results in more accurate capacitive values. >

DC to DC converter using quasi-resonance

Abstract: A quasi-resonant DC to DC converter having zero-current and zero-voltage switching includes a transformer with primary and secondary windings, and periodic switching means connected in series with the primary winding. The converter further includes an input capacitor parallel to the transformer's primary winding and an output capacitor parallel to the secondary winding. The topology of the converter is determined by selecting an input capacitor having a capacitance much lower than the output capacitor, by selecting the resonance period of a circuit including the input capacitor and the overall series inductance of the transformer to be shorter than the ON period of the periodic switching means, and by selecting the resonance period of a circuit including the overall parasitic capacitance, referred to the primary side of the transformer and the periodic switching means, and the magnetizing inductance of the transformer to be shorter than the OFF period of the periodic switching means.

Imaging system employing charge amplifier

Abstract: A system 10 for imaging radiation received from a scene provides for the focusing of the radiation upon a set of detectors 12. A set of amplifiers 14 couple the detectors to an image processor 24 for forming an image of the scene. The amplifiers are pulsed with a repeating sequence of pulses providing sequential operation of the amplifiers. The amplifiers and the detectors are constructed on a single substrate which is cyrogenically cooled for improved signal-to-noise ratio. Amplifying elements in each of the amplifiers are powered by energy stored as electric charges in capacitors. The capacitors are recharged with pulses from a pulsing unit repetitively in a repeating sequence of amplifier operation. The capacitors provide for integration of detector signals, there being additional integration performed at the front end of each of the amplifiers utilizing stray capacitance and detector capacitance. Adjustment of front end voltage of each of the amplifiers permits compensation for nonuniformities among the detectors. There results an improved signal-to-noise ratio which can be optimized for different sampling rates of incoming radiation signals.

Effects of deep imperfection levels on the capacitance of semiconductor detectors

Abstract: A general theory capable of describing the capacitance of a surface-barrier or a junction detector is presented. Particularly the effects of deep imperfection levels in the semiconductor material on the capacitance vs frequency and the capacitance vs bias voltage characteristics of a detector are considered. Several important features of the detector capacitance measurements are pointed out. The results of the detector capacitance measurements available in the literature and those obtained by us are discussed.

Parasitic capacitance effects of planar resistors

Abstract: The intrinsic capacitance of a planar resistor in a hybrid circuit is discussed. Basic theory is outlined to model the self-capacitance effect of resistive layers. A perturbation method is derived where the zeroth order accounts for the pure resistive effects and the first-order perturbation deals with the capacitive effects. It is shown that even in the absence of contact electrode capacity, any resistive layer creates a capacitive field in the substrate and the surrounding materials. A model is made to describe these intrinsic capacitance effects, and some numerical results are shown. >

Shielded capacitance standard

Abstract: This invention relates to a capacitance standard for use with capacitance sensitive probes. The standard comprises a capacitor having a pair of spaced plates and a dielectric positioned therebetween. A shield attached to one of the plates forms an enclosure around the other plate to essentially shield the capacitor. The capacitance standard is therefore not affected by outside electrical fields and an accurate, reproducible capacitance value is provided.

A new address scheme to improve the display quality of a-Si TFT/LCD panels

Abstract: A drive scheme for a-Si thin-film-transistor/liquid-crystal-display (TFT/LCD) panels that cancels out the DC voltage of the pixel electrode is described. This addressing scheme comprises a three-level gate pulse and an additional capacitor. The gate pulse level has opposite polarity to the conventional two levels and plays a role in compensating the DC voltage caused by the parasitic capacitance of a-Si TFT panels. The compensating voltage is introduced through an additional capacitor fabricated between a pixel electrode and the next gate line. This method is successfully introduced to a 5-in.-diagonal panel, and improvement of the display quality is observed. The latent image is reduced by this addressing scheme, as is flicker noise. The relation between DC voltage and the latent image is clearly recognized in the display panel. The mechanism of flicker noise caused by DC voltage is also discussed. >