Showing papers on "Parasitic capacitance published in 1990"

A capacitive pressure sensor with low impedance output and active suppression of parasitic effects

Abstract: This paper describes the design, operating principles and performance of a capacitive pressure sensor in silicon, combined with a dedicated CMOS interface circuit. The readout circuit is designed to suppress parasitics and to yield an output signal proportional to pressure. The sensor-specific part is fabricated using standard photolithography, silicon micromachining in KOH, and anodic silicon/glass bonding at wafer level. The devices measure 2.2 × 3.5 × 0.8 mm and show a typical zero-pressure capacitance of 10 pF, with pressure-induced changes up to 250%. The interface chip ‘CAPRICE’ (CApacitive Pressure sensor Readout IC) is processed in a 3 μ n-well CMOS process and was designed to anticipate the intrinsic drawbacks of the capacitive transducing principle, i.e. sensitivity to environment noise, nonlinear output response and effects of parasitic capacitances. These drawbacks have always prevented the breakthrough of integrated capacitive mechanical sensors. CAPRICE, however, converts small capacitance variations into a noise-insensitive output voltage and a first-order linearisation is achieved by inversion of the hyperbolic capacitance versus pressure relationship. A second-order linearisation is obtained by the adoption of a novel suppression scheme for parasitic capacitances to the substrate. Parasitic capacitance rejection ratios up to 80 dB can be achieved in this way, enabling the practical feasibility of capacitive pressure sensors with less than 0.5% of full-scale nonlinearity.

Proximity responsive capacitance sensitive method, system, and associated electrical circuitry for use in controlling mechanical and electro-mechanical equipment

Abstract: A method and system and associated circuitry for controlling and stopping the motion of dangerous moving parts such as power saw blades substantially instantaneously in response to body or human capacitance produced by an operator coming with a predetermined critical distance from the moving part. This method includes, and this system provides for, among other things, connecting an antenna to the moving part and then coupling a tunable circuit to the antenna so that the antenna provides a variable lumped capacitance parameter (dependent upon human body capacitance) within the tunable circuit. This lumped capacitance parameter is variable in response to body or human capacitance produced when an operator comes within a predetermined critical proximity to the moving part. This variation in lumped capacitance serves to tune the circuit at or near a point of resonance to thereby enable an RF signal to pass through the tunable circuit at a detectable level which is subsequently processed to activate safety equipment for controlling and stopping the motion of the moving part substantially instantaneously. This invention is also adaptable for use with non-dangerous mechanical apparatus such as automatic door openers, automatic robot equipment, and capacitance-sensitive lighting appliances, and the like. It is also adaptable for use on automobile safety equipment, such as the proximity sensing of persons approaching an automobile out of the normal line-of-sight vision angles of the driver.

A micron-thickness, planar Schottky diode chip for terahertz applications with theoretical minimum parasitic capacitance

Abstract: The design and fabrication of a novel planar Schottky diode with greatly reduced shunt capacitance for millimeter- and submillimeter-wave applications is described. The dominant pad-to-pad shunt capacitance is minimized by replacing the substrate GaAs with a low-dielectric substitute. This replacement substrate can be easily removed by the user after the device is soldered into the mixer circuit. This will yield the minimum possible pad-to-pad shunt capacitance. >

Linearized capacitance sensor system

Abstract: A capacitive sensing circuit and system includes a variable capacitance sensing element as an active element in a circuit to measure changes in capacitance of the sensing element. A switching network in alternate cycles energizes a capacitor to develop a charge which effectively linearizes the sensor's capacitance response. In a push-pull circuit with two active sensing elements, a multi-channel switching network energizes two fixed correction capacitors to provide third or higher order correction, significantly extending the effective scale of the sensor. In a preferred embodiment, a single feedback signal is applied to all capacitors in different switching cycles. Examples include weight and pressure sensing systems.

High-frequency operation of a planar-type microtransformer and its application to multilayered switching regulators

Abstract: The operation of a multilayered microtransformer composed of planar zig-zag coils and amorphous magnetic film is described. The transformer has a maximum efficiency of 77.5%. Its equivalent circuit is approximated by the parallel connection of the winding inductance and of the stray capacitance. Variable magnetic coupling is obtained between the primary and secondary windings by shifting the relative position of the two coils. The microtransformer is used in a magnetically controlled multilayered switching regulator. The regulator has an output of 1.4 W and an efficiency of 24%. The magnetization loss in the circuit is the same as that of the semiconductors. A two-output-type multilayered switching regulator is also proposed that has an acceptably good output characteristic at each port even though a common magnetic film is used. >

Measurement of small capacitance variations

Abstract: A technique for measuring low-frequency and low-level capacitance variations is proposed. It is based on a lock-in detection circuit with a feedback loop, containing an integrator and a modulator for zeroing the capacitance mean value. This approach provides a good signal-to-noise ratio and high sensitivity. Capacitance variations can be on the order of 100 p.p.m. of the mean value, and the frequency of the variations can be as low as 0.1 Hz. Stray capacitances and the drift due to the environmental conditions are automatically compensated. The measurement technique, experimental apparatus, and initial results are described. Small variations, about 10 fF, have been measured in the presence of 10-pF mean value. >

Low-parasitic, planar Schottky diodes for millimeter-wave integrated circuits

Abstract: The design and fabrication of air-bridged, ultra-low-capacitance Schottky barrier diodes are described. Mott diodes, for mixer applications, and varactor diodes, for use in frequency multipliers, have been produced simultaneously on epitaxial wafers grown by molecular beam epitaxy. Typical mixer diodes have a nominal anode contact area of 4 mu m/sup 2/ and exhibit a total zero-bias capacitance of 4.0-4.5 fF (including a parasitic capacitance of approximately 1.0 fF) and a series resistance of 6-8 Omega . Diode chips have been incorporated in hybrid integrated circuit (MIC) mixers for 33-50 GHz and 75-110 GHz and an MIC frequency tripler for 90-140 GHz. Fully monolithic (MMIC) subharmonically pumped mixers for 75-110 GHz have also been fabricated and tested. >

Differential relaxation oscillator

Abstract: A relaxation oscillator is disclosed which includes first and second currents for charging and discharging a capacitor (50) wherein the slew rate of the dynamic voltages developed at the terminals of the capacitor (50) remain substantially constant for each frequency of operation which desensitizes the oscillator to the effects of the inherent stray capacitance, and improves the accuracy of the output frequency. A circuit (74,76,78,80) monitors the dynamic voltage across the capacitor (50) and inverts a control signal at opposite polarities of a particular threshold. A bistable circuit (86,88,90,92,94) provides first and second complementary output signals in response to the control signal from the circuit (74,76,78,80). The first and second complementary output signals drive a pair of switching transistors (52,54) which alternate the direction of current flowing through the capacitor (50) so as to provide smooth voltage transitions at the terminals of the capacitor (50).

Precision capacitive transducer circuits and methods

Abstract: A method and means for determining the deflection of a movable element in a transducer by measurement of capacitance. The result is independent of extraneous capacitance between the transducer terminals and the environment, of the magnitude of the transducer capacitance, and of scaling factors within the measurement circuits. The difference and sum of differential capacitances are determined, preferably independently of their individual values, using switching techniques and a common measurement circuit. The ratio of differential capacitances is determined by causing the measurement signal for one capacitance to be inversely proportional to the magnitude of the other capacitance.

Dynamic random access memory having stacked capacitor structure

Abstract: A DRAM has a memory cell array in which a plurality of word lines (WL) and a plurality of bit lines (B0) are arranged to orthogonally intersect each other. Memory cells (MC) are arranged in a direction intersecting the bit lines. Capacitors (10) of the memory cells are arranged between the adjacent bit lines. On a silicon substrate (20), the bit line is formed substantially at the same height with the word line and positioned lower than the top of the capacitor. An opening region (15) is formed so that electrode layers (11, 13) of the capacitor do not cover the bit line. The arrangement of the capacitors between the adjacent bit lines allows reduction in the inter-bit-line capacitance. In addition, formation of the region above the bit line which is not covered by the electrode layers of the capacitor makes it possible to reduce the stray capacitance between the capacitor and the bit line. As a result, reduction in amount of the read-out signals which might be caused by an increased bit-line capacitance can be prevented.

A high power 2-18 GHz T/R switch

Abstract: A high-power 2-18-GHz T/R (transmit/receive) switch monolithic microwave IC (MMIC) has been developed for use in broadband T/R modules. This switch has a power handling of better than 35 dBm (3.2 W), 8-dB higher than any previously reported broadband switch. A combination of techniques was used to yield higher power handling while preserving low loss and high isolation. These circuit techniques include an asymmetrical design of the transmit and receive arms, the use of dual-gate FETs for handling large voltages, and the use of large FET peripheries for handling large currents. The use of dual-gate FETs in place of a stack of individual FETs reduces the device area, with a resulting reduction in parasitic series inductance through the FET and in shunt capacitance from the FET to ground. Power handling is somewhat lower for the dual-gate FET than for conventional stacked FETs, since RF voltage cannot be distributed as uniformly across the gates. Offstate capacitance is higher for a dual-gate FET than for a stacked FET, since the close proximity of the elements leads to additional parasitic capacitances. >

A low-power wide-band amplifier using a new parasitic capacitance compensation technique

Abstract: A 3-mW 800-MHz amplifier with a voltage gain of 10 dB is discussed. The parasitic junction capacitance of a transistor is the major factor limiting the bandwidth particularly for low-power amplifiers. In addition to the pole at the input node, the pole at the output node may become dominant in low-power amplifiers, which use high-speed bipolar transistors. A parasitic capacitance compensation technique to expand the bandwidth in this type of amplifier is discussed. This technique compensates for both capacitances at the input and output nodes and enhances the bandwidth and the gain-bandwidth product. The measured data demonstrate that this technique expands the bandwidth to about twice that of a conventional differential amplifier. In addition, circuit simulation predicts that this technique expands the bandwidth by about 40% over a conventional peaking technique. A stable frequency response without any overpeaking or oscillation problem has been achieved by utilizing the parasitic junction capacitances of dummy transistors as the compensation capacitance. >

A ULSI 2-D capacitance simulator for complex structures based on actual processes

Abstract: A two-dimensional (2-D) capacitance simulator for ultra-large-scale integrated (ULSI) circuits using an improved boundary-element method (BEM) is described. The capacitance simulator was linked with a topography/process simulator to estimate the distributed capacitances of complex structures based on actual processes. The utilization of a linear discontinuous element as the shape function is proposed in order to deal with multiregional problems by BEM. Other techniques employed in the simulation program, which enable precise calculation within practical CPU time, are also described. The calculated capacitances show good agreement with the experimental results. >

Monolithic lumped element networks

Abstract: An RF circuit which may be for example a high pass filter, low pass filter, phase shifter, bandpass filter, termination network, bias network, or series or parallel resonance circuit includes at least one strip conductor coiled about a region and an outer or ring strip conductor disposed about a periphery of the at least one coiled strip conductor and coupled to said at least one coiled strip conductor through a dielectric. Parasitic capacitance between the coiled conductor and outer or ring conductor provide capacitor elements for the circuit.

On-chip quasi-static floating-gate capacitance measurement method

Abstract: An accurate interconnect capacitance parameter measurement technique is described. The technique is based on measurement of a capacitively divided DC voltage by means of a source follower stage integrated in the test structure. Determining of dielectric thickness as well as interconnect capacitance parameters using this technique in combination with special test patterns is described. The method shows good agreement with two-dimensional computer simulations. The technique is proven to be practical, reliable, and suited for use with manual and automatic parametric test equipment. >

Shared BiCMOS sense amplifier

Abstract: A switching circuit for SRAM memory cells is disclosed. The circuit electronically decouples input lines to sense amplifiers from unselected arrays of memory cells. The decoupling results in a large decrease in the amount of parasitic capacitance that the selected inputs would encounter.

Capacitance height gauge

Abstract: A capacitance-type height gage for measuring the distance between a test probe and a surface includes comparison circuitry for detecting the phase angle difference between the test probe signal and a reference signal. The reference signal having an adjustable phase angle. Phase angle comparison is achieved by multiplying the test probe signal with the reference signal and filtering the output. The filtered output is inversely proportional to the distance between the test probe and the surface. Compensation circuitry is included for cancelling stray capacitance.

DC/DC switching converter circuit

Abstract: A two switch, DC/DC converter provides sufficient inductive energy storage at the termination of the "on" period of each switch to alter the charge on the intrinsic and stray capacitance of the combination of switches producing zero voltage across the alternate switch prior to its turn on. A short dead-band between the turn on pulses provided by the control circuit allows time for this transition. Thus the energy stored in the capacitance of the switches is returned to the source and load rather than being dissipated in the switching devices. This greatly improves the efficiency of the converter particularly when operating at high frequency. The unique topology of the converter provides other new and useful characteristics in addition to zero voltage switching capability such as operation at constant frequency with pulse-width-modulation for regulation, quasi-square wave output current, and the ability to integrate the magnetic elements with or without coupling.

An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

Abstract: An internal erase and erase-verify control system implemented in all electrically erasable, reprogrammable, 80-ns, 1-Mb flash memory suitable for in-system reprogram applications is discussed. This system features a command signal latch, a sequence controller, and a verify voltage generator. Timing in the electrical erase mode is shown. The erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers, as well as from low-resistance polysilicide word lines and scaled periphery transistors. For sensitivity and speed of the sense circuits, a pMOSFET with gate connected to drain is used as a load transistor. Compared with a conventional sense amplifier with a grounded-gate pMOSFET load, the shorter channel length of the pMOSFET used here gives the same sensitivity, reducing the stray capacitance problem. Together with a signal voltage swing reduced by a threshold voltage of the pMOSFET, this is essential for access speed. Simulation shows a 30-ns reduction of access time at a V/sub cc/ of 4.25 V. Schmoo plots of the address access time indicate that V/sub cc min/ is 3.4 V, demonstrating the proper operation of the automatic erase scheme. >

Device Models, Circuit Simulation, And Computer-controlled Measurements For The IGBT

Abstract: The implementation of the recently dcvel- oped IGBT device model into a circuit simulation program is described. It is shown that the circuit simulation program rapidly and robustly simulates the dynamic behavior of the IGBT for general external drive, load, and feedback circuit configurstions. The algorithms used to extract the IGBT de- vice parameters from computer-controlled measurements are also described, and it is shown that the model accurately de- scribes experimental results when the extracted parameters are used.

Triple-resonance pulse transformer circuit

Abstract: A modified, resonant pulse transformer circuit, based on a generalization of the well‐known double‐resonance pulse transformer circuit, is described. This modified circuit allows complete energy transfer in the presence of non‐negligible internal capacitance of realistic pulse transformers, and substantially reduces peak transformer voltage, compared to the double‐resonance circuit. Conditions under which the internal capacitance significantly affects energy transfer, and sensitivity of overall efficiency to circuit component values are discussed.

Electronic circuit device for protecting electronic circuits from unwanted removal of ground terminal

Abstract: An electronic circuit device having a protection circuit for protecting a switching system electronic circuit when a ground terminal is removed from the device. The protection circuit includes a detection circuit for detecting the ground terminal has been removed from ground as a change in an electronic potential of the ground terminal, an input cut-off circuit connected between an input terminal and the electronic circuit to control an operation of the electronic circuit, a low voltage protection circuit for controlling an operation of the electronic circuit in response to an output signal from the detection circuit, and a memory circuit for controlling an operation of the input cut-off circuit in response to both output signals from the detection circuit and the low voltage protection circuit.

Two-stage resonant starting circuit for an electrodeless high intensity discharge lamp

Abstract: A starting circuit for an electrodeless HID lamp provides a two-stage resonant starting signal to a gas probe starter of the type comprising a starting chamber which contains a relatively low-pressure gas and is attached to the outer wall of the arc tube. The starting circuit comprises a resonant LC circuit of variable impedance including the series combination of a variable inductance and the parasitic capacitance between the gas probe starter and the excitation coil. In operation, the resonant circuit is tuned to a predetermined value so that, upon application of an RF signal to the excitation coil, resonant operation of the starting circuit results in the application of a sufficiently high starting voltage to the starting chamber to ignite a low-current glow discharge therein. Once the glow discharge is ignited, the starting circuit is retuned to ensure that a sufficiently high starting voltage is capacitively coupled to the arc tube to ionize the arc tube fill and initiate an arc discharge therein.

Correction procedure of the phase difference introduced by a zero sequence toroid of leakage current and isolation monitor this procedure

Abstract: A digital isolation monitor comprises a signal processor operating in conjunction with a measuring circuit to perform a first no-load measurement and a second load measurement of a zero sequence signal delivery by a toroid of a differential transformer, followed by synchronous demodulation, A microcontroller computes the tangent of the angle of phase difference introduced by the toroid by computing the relationship between the load and no-load components, and determines the true values of the leakage resistance and stray capacitance of the power system.

Effects of the lightly doped drain configuration on capacitance characteristics of submicron MOSFETs

Abstract: Measurements and simulations show that an LDD (lightly doped drain) configuration has a considerable effect on MOSFET capacitance characteristics. The effects have been included in a circuit-level capacitance model in an explicit form, avoiding the need for extra nodes in the MOSFET model. The presented model yields clearly improved accuracy. >

Delay circuit for integrated circuit

Abstract: A delay circuit for integrated circuits includes a current mirror circuit having at least a pair of MIS transistors, a constant current source and a capacitance. The delay time is determined by the charging time of the capacitance connected to one of the MIS transistors. A stable delay time is obtained regardless of manufacturing variations and the space required for the circuit is reduced.

Common-mode error self-calibration circuit and method of operation

Abstract: There is disclosed a fully differential converter (10) having a very high common mode rejection ratio. The capacitive parasitics (CP) are accounted for by a strategic placement of error correction capacitances (20). The actual value of the capacitance is calculated from time to time by successively making comparative circuit operations and by adding and subtracting capacitance automatically under logic control (62) until the circuit is in near balance. The final value of the added capacitance for any given calculation set is stored in a memory (61). In this manner the circuit become self-calibrating and common mode rejection ratios over 90 db are possible.

Static memory containing sense amp and sense amp switching circuit

Abstract: A static memory cell is connected with word lines and data lines. First and second switches are connected in series between a data line and an output circuit. A sense amplifier has an input/output terminal connected to a common connection point of the said first and second switches. The first switch is turned off in synchronism with commencing operation of the sense amplifier such that the parasitic capacitance of the data line as viewed from the sense amplifier decreases. The second switching means is turned on a predetermined time later in order to transmit the output signal of the sense amplifier to the output circuit.

A new planar inductor with ring-connected magnetic core

Abstract: A planar inductor employing a ring-connected magnetic core has been devised. By connecting small planar ring cores in a matrix array, the magnetoresistance of the magnetic circuits in the core is reduced, and high inductance, which is about 1.5 times that of the conventional ring-core inductance, is achieved. By exciting the core with two coils arranged orthogonally, the stray capacitance, which restricts the upper limit of the useful frequency band, is decreased. The inductor is suitable for a microinductor operating at high frequency. The ring-connected core can be also used as a transformer with high coupling coefficient and low stray capacitance. >