Showing papers on "Parasitic capacitance published in 1991"

High-voltage, high-power, ZVS, full-bridge PWM converter employing an active snubber

Abstract: The authors present the analysis, design, and applications of a high-voltage, high-power, zero-voltage switched (ZVS), full-bridge (FB) pulse-width-modulated (PWM) converter with an active snubber in the secondary circuit. The nondissipative snubber completely eliminates the voltage overshoot and ringing across the rectifiers. The ringing of the parasitic capacitance of the rectifiers and the leakage inductance of the transformer are eliminated in a nondissipative manner, thus increasing the overall efficiency of the circuit. The active snubber employs only a high-voltage low-power MOSFET and a high-voltage capacitor. The control of the snubber switch is simple and utilizes the PWM signal to control the primary switches with a time delay. The authors also present the complete steady-state analysis of the ZVS-FB-PWM converter employing the active snubber. The analysis shows that the transformer secondary voltage is a function of the steady-state duty cycle and gives the equation to calculate the steady-state secondary voltage. The results of the analysis are in good agreement with the experimental results. >

RICE: Rapid interconnect circuit evaluator

Abstract: This paper describes RICE, an RLC interconnect evaluation tool based upon the moment-matching technique of Asymptotic Waveform Evaluation (AWE). The RLC circuit moments are calculated by a path-tracing algorithm which enables the analysis of large interconnect models several thousand times faster than a circuit simulation while requiring 5 to 10 times less memory. RICE also includes a new approach for determining the circuit dominant time-constants which avoids the inherent instability problems associated with moment matching methods in general.

Printed circuit board having an integrated decoupling capacitive element

Abstract: A printed circuit board is disclosed which includes a high capacitance power distribution core, the manufacture of which is compatible with standard printed circuit board assembly technology. The high capacitance core consists of a ground plane and a power plane separated by a planar element having a high dielectric constant. The high dielectric constant material is typically glass fiber impregnated with a bonding material, such as epoxy resin loaded with a ferro-electric ceramic substance having a high dielectric constant. The ferro-electric ceramic substance is typically a nanopowder combined with an epoxy bonding material. The resulting capacitance of the power distribution core is typically sufficient to totally eliminate the need for decoupling capacitors on a typical printed circuit board.

Design of a high-frequency planar power transformer in multilayer technology

Abstract: A high-frequency power transformer using multilayer printed circuit board (ML-PCB) technology is presented for applications in switched-mode power supplies operating at frequencies up to several megahertz. The mechanical configuration of laboratory prototypes is discussed, as well as the electrical, parasitic, and thermal behavior. The focus is on the leakage inductance, since the analysis of other aspects is relatively simple. Test results show that the transformer has high efficiency, low leakage inductance, good thermal behavior, and good line insulation properties. The topology enables the designer to make a trade-off between leakage inductance and interwinding capacitance. Due to the well-defined geometry, parasitic interwinding capacitance and leakage inductance are reproducible and can be computed relatively easily. >

A 10-b 40-MHz 0.8- mu m CMOS current-output D/A converter

Abstract: A 10-b binary-weighted D/A digital-to-analog converter based on current division is presented. The effective resolution bandwidth is 5 MHz at a maximum clock frequency of 40 MHz. The circuit is integrated in a 0.8- mu m double-metal CMOS technology and the chip area is 0.4 mm/sup 2/. This particular converter was realized by constructing the bit currents through a careful combination of unit current sources and by limiting the driving voltage on the gates of the current switches. >

Probe for measuring surface roughness by sensing fringe field capacitance effects

Abstract: A capacitance sensing probe is disclosed for taking measurements of features on a workpiece surface. The probe has two electrodes (E 1 , E 2 ) spaced apart in the direction of movement of the probe with the electrodes being disposed in an attitude normal to the surface. Only the edge of the electrodes are exposed to the surface and an electric circuit (EC) is provided for determining the effect of the surface on the fringe field capacitance between the electrodes. Guard electrodes are used to reduce the stray capacitance being measured. Various embodiments are shown with different numbers and arrangements of electrodes.

Analysis of stray capacitance in the Kelvin method

Abstract: We present a theoretical analysis of the Kelvin probe circuit taking into account both the parallel capacity induced by the connecting cables and fringing fields. We demonstrate a simple explicit solution for low modulation index e and suggest an optimized detection method for e close to unity. We extend the analysis to include stray capacitance terms for both the static‐ and vibrating‐plate earthed (spe, vpe) configurations and examine the variation in apparent contact potential difference Vapp as a function of the Kelvin probe mean spacing. This analysis is primarily intended for UHV applications where shielding problems, due either to connecting cables within the system or nonideal system configurations, e.g., imposed by sample mounting constraints, are nontrivial. Using a specially developed computer‐steered Kelvin probe and shield potential Vs coupled to a data acquisition system (DAS) we have tested the above model. We find Vapp to be linear with Vs and varies quadratically with mean spacing in both...

Analysis of the inductance and the stray capacitance of the dry-etched micro inductors

Abstract: Thin film inductors with meander coils or spiral coils were examined systematically. The minimum line spacing of the inductors was 1.5 mu m. In case of air core inductors, both inductance and stray capacitance were calculated from the dimension of the inductors, and they agreed well with measured values. With the application of a magnetic thin film, the inductance is increased and the degree of increase was proportional to the length of the coil. It is found that the capacitance between conductor and magnetic film is very significant and needs special consideration. >

Mismatch sensitivity of a simultaneously latched CMOS sense amplifier

Abstract: Derives a new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in dynamic-RAMs (DRAMs), to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bit-line load capacitance mismatch. The formula yields insight into the DRAM sensing operation. The authors derive a sensitivity formula for this sensing scheme, using perturbation theory. The perturbation approach is rigorous: it avoids most approximations and ad-hoc assumptions, it introduces no free constants to be determined from simulations, and it yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design. >

Switch-level timing simulation based on two-connected components

Abstract: A method for simulating a transistor circuit determines which nodes in the circuit change state in response to events, and then accurately computes the times at which those nodes change states. Using parasitic capacitance and transistor conductance values extracted from the circuit layout, this method and evaluates driving-point resistances and delays in an RC-network representation of the complete circuit.

A new MOS imager using photodiode as current source

Abstract: The author presents a MOS linear image sensor having a high-voltage gain amplifier in photodiode pixels. The only difference between the amplified MOS image (AMI) and this new device is the transfer gate added between the photodiode pixel and the source follower. In this structure, the photoinduced charge loss in video-line parasitic capacitance is compensated to improve the sensitivity. A high-voltage-gain amplifier is used to control the input voltage of the transfer gate so as to maintain an unchanged bias voltage of the photodiode and by operating the photodiode cell as a current source. In this device, the photoinduced charge is not divided by the photodiode capacitance C/sub d/ or the capacitive load C/sub t/. Therefore, it is possible to enlarge the photodiode size, and the sensor has a large saturation exposure as well as a large photocurrent/dark-current ratio of about 30:1. The device operates on a single 5 V power supply. These features make the device suitable for applications in low light levels. >

RF performance of a novel planar millimeter-wave diode incorporating an etched surface channel

Abstract: A whiskerless millimeter-wave mixer diode that yields performance comparable to that of the highest-quality whisker-contacted diodes is discussed. The diode uses an etched surface channel and planar air bridge to obtain greatly reduced parasitic capacitance. At 94 GHz, the room-temperature diode exhibited a conversion loss of 5.3 dB+or-0.5 dB and an equivalent input noise temperature of 518 K+or-50 K SSB (single sideband). >

Electrostatic of wound components: analytical results, simulation and experimental validation of the parasitic capacitance

Abstract: The electrostatic properties of inductors and transformers are investigated. Two devices have been built on the same magnetic core. Both are cylindrical coaxial winding transformers and all the windings are almost identical. These one-layer windings are rolled in the same direction for one transformer and in opposite direction for the other. All the possible connections of the two windings are tested. Based on a simple electrostatic model, these devices are analytically studied and an equivalent circuit is proposed to take electrostatic phenomena into account. Then, an electromagnetic simulation software is used to compute the electrostatic field with the real shapes of wires and coil layers. Capacitances are deduced from stored electrostatic energy in the whole space. Finally, many impedance measurements from 100 Hz to 40 MHz allow the equivalent circuit to be validated.

Retarded models for PC board interconnects-or how the speed of light affects your SPICE circuit simulation

Abstract: It is shown that retardation effects, due to the finite speed of electromagnetic interactions, play a significant role for PC-board interconnects. It is demonstrated that in some cases errors of more than an order of magnitude result in some frequency components when retardation is neglected. Extensions to a circuit simulator are introduced that make it possible to do retarded circuit simulation. Specifically, an algorithm to extend SPICE-level simulators to include retardation is presented. Comparisons with analytical equations, the method of moments, and with measurements show good agreement. >

Simple sub‐50‐ps rise‐time high voltage generator

Abstract: This article relates to the development of an ultrafast (nanoseconds–picoseconds time scale) compact system(s) readily applicable to the field of EMP/radiation, x‐ray‐induced nondestructive testing, plasma fusion (energy) experiments, bioelectromagnetic (food‐drug) sterilization, drivers for x‐ray preionized XeCl laser and similar applications. The present work shows that the Marx and the Pulse forming section can be integrated into a single unit. The stray capacitance present in each stage acts as a peaking capacitor. For a charging voltage per stage of <40 kV, the rise time of the output pulse is below 50 ps at 200 kV into a 100‐Ω load. Work is in progress to extend the voltage amplitude to 1.6 MV while maintaining the relative pulse waveform. With a contemporary optical diagnostic technique it is believed that the present concept may achieve 1–10 ps rise‐time pulses at a megavolt level in ‘‘smart gas mixtures.’’ In addition a solution for the classical peaking circuit has been obtained and presented in...

Variable-capacitance position transducing

Abstract: A variable-capacitance transducer detects the angular position of a rotatable member. The transducer includes a first capacitance plate having a plurality of electrically conductive capacitance electrodes, a second capacitance plate spaced therefrom, and a dielectric element located between the plates. At least two of the electrodes are interconnected by a conductive trace. The dielectric element or one of the plates is fixedly mounted on the rotatable member. The electrodes on the first capacitance plate, in conjunction with the second capacitance plate, form a plurality of capacitances that vary as the angular position of the rotatable member changes. A conductive guard partially envelopes the conductive trace and a conductive guard partially envelopes the electrodes on the first capacitive plate. A spacer defines the distance between the capacitance plates and has a coefficient of thermal expansion and dimensions that cause the distance between the capacitance plates to vary by an amount calculated to compensate for changes in plate area with temperature. The transducer includes a parasitic capacitor plate having a position that is adjustable to compensate for parasitic capacitance. An electromagnetic shield is constructed and positioned, with respect to a driver that controls the rotatable member, such that the shield tends to prevent electromagnetic radiation from the driver from affecting the capacitances between the capacitance plates.

High frequency linear amplifier assembly

Abstract: A wide bandwidth linear amplifier (10) that has an operating band in excess of 1 GHz mounts the high power dissipating components (11) of the amplifier (10), and the components 917, 18) that control the high frequency gain and stability of the amplifier (10) onto a daughter board (32) that has a high thermal conductivity The daughter board (32) and the remaining circuit components (21, 22, 23, 24, 26a, 26b) are then mounted on a mother board (31) that has a lower thermal conductivity The assembly (30) reduces the circuit's parasitic inductance (46, 47, 48, 49) and parasitic capacitance (51, 52), and provides unconditional stability at high frequencies

Integrated circuit dual-port memory device having reduced capacitance

Abstract: A dual-port memory device provides for a memory array which is divided approximately in half. Between the two halves of the array, a bit line crossover scheme is provided which minimizes stray capacitance and cross-coupling capacitance between bit lines for the two different ports. A bit line layout plan which minimizes such capacitances causes the data for one of the ports to be inverted in one-half of the array. When data from this half of the array is read or written by such port, the data being read or written must be inverted.

Low power optoelectronic device and method

Abstract: Methods and devices are disclosed for selectively varying the load to a photodetector such as a phototransistor which forms part of a photosource/photodetector pair and for selectively using to advantage or compensating for the parasitic capacitance of the photodetector to permit reductions in power, conversion of fixed signal thresholds to software controlled digital hysteresis, automatic adjustment and compensation for unmatched photosources and associated photodetectors, and adjustment of fixed voltage thresholds.

Capacitive probe sensor with reduced effective stray capacitance

Abstract: A capacative probe is provided which has reduced effective stray capacitance and is thus able to accurately detect probe contact with a conducting fluid with small fluid volumes. Effective stray capacitance is reduced by dividing stray capacitance sources into two or more sources, by reducing the capacitance value of each of the divided stray capacitance sources to a value which is substantially less than the capacitance difference which occurs as a result of probe contact with the fluid and by connecting at least selected ones of the divided stray capacitance sources in series to further reduce effective stray capacitance. The capacitance value of the stray capacitances are reduced by providing a gap in a conducting tube covering the probe aspirating tube, which gap isolates conductive elements of the probe from the probe tip potential, thus reducing or eliminating the potential across various stray capacitance sources (and thus reducing or eliminating such sources) and also results in reduced plate sizes for such stray capacitance sources. A capacitance across the gap, which may be of a controlled small value, is also in series with selected stray capacitance sources, further reducing the effective stray capacitance of the probe.

Low-loss resonant circuit for capacitance driver

Abstract: A fast lossless power MOSFET gate capacitance (C) driver uses a 3-winding transformer (T) to secure clamping (N, Vc, D) of the turn-on voltage level by coupling of the winding (N1) in the capacitance charging circuit to that (N) across the clamping potential (Vc) in series with a clamping diode (D). A similarly coupled winding (N2) in the discharging circuit can ensure clamping of the turn-off level, both rise and fall starting at zero current and being sinusoidal. Alternatively, a high Q constant current charge can be used with the charging circuit switch (S1) DC isolated from the capacitance and using the magnetising current built up in the transformer. Instead of clamping the turn-off level, the discharging circuit can be switched (S2) during magnetising current build-up (S1) using a separate inductance to reverse the capacitance voltage in a half-wave resonant circuit.

Capacitance and leakage test method and apparatus

Abstract: Capacitance is measured using a system including a high voltage ramp monitor A signal net is connected to ground by probes while a constant charging current is applied to the internal planes A pure capacitive net will have a linear voltage rise proportional to capacitance, therefore its capacitance can be represented by ramp time Leakage shorts will be detected by residual charge current measurements The stimulus voltage is maintained for a fixed time after ramping to provide net to internal plane stress testing Measured net capacitance is compared to nominal net capacitance for short/open detection

Application of YIG film to thin film inductors

Abstract: The application of YIG (yttrium iron garnet) films to thin film inductors is examined up to 1 GHz The application of a YIG film to thin film inductors made it possible to increase the inductance without increasing the stray capacitance The sandwich-type YIG inductor exhibited an inductance 40 times larger than that of a similar air core inductor The inductance of this type of inductor was calculated using the reluctance of a magnetic circuit which locally surrounds the cross section of each conductor >

Analysis of shielded CPW discontinuities with air-bridges

Abstract: The effect of air-bridges on the performance of various coplanar waveguide (CPW) discontinuities is studied. Specifically, the coupled open-end CPWs and the short-end shunt CPW stub discontinuities are considered. The high-frequency effect of the air-bridge is evaluated using a hybrid technique. First, the frequency-dependent equivalent circuit of the planar discontinuity without the air-bridge is derived using the space domain integral equation method. Then, the circuit is modified by incorporating the air-bridge's parasitic inductance and capacitance, which are evaluated using a simple quasi-static model. The frequency response of each discontinuity with and without the air-bridge is studied, and the scattering parameters are plotted in the frequency range 30-50 GHz for typical CPW dimensions. >

Design considerations for common-mode feedback circuits in fully-differential operational transconductance amplifiers with tuning

Abstract: Power consumption, chip area, feedback loop gain, parasitic capacitance and nonlinearity of three popular common-mode feedback (CMF) circuits used in operational amplifiers are analyzed and compared. One of them is chosen as a candidate for CMF in fully differential operational transconductance amplifiers (OTAs). Three improved versions of this circuit that can be used in an OTA without leading to DC offset caused by the always unavoidable tuning are proposed. Simulation results show that the improved circuits reduce the DC offset from 0.6 V to nearly zero for the whole tuning range. >

Capacitance sensor circuit and method for measuring capacitance and small changes in capacitance

Abstract: An improved oscillator circuit and method for measuring capacitance and small changes in capacitance is described The circuit provides a digital output signal that has a frequency inversely proportional to the capacitance being measured, is substantially immune to stray capacitance, has low sensitivity to noise and temperature variations, is relatively simple and inexpensive to implement and provides a high precision measurement One embodiment of the oscillator includes a capacitor to be measured, an integrator, an inverting amplifier, a comparator, a summing amplifier and a digital output circuit A second embodiment of the oscillator further provides compensation for the non-linear response of a parallel plate capacitive transducer

Design of a broadband microwave BJT active inductor circuit

Abstract: The synthesis and S-parameter analysis of a novel broadband microwave active inductor circuit utilizing bipolar junction transistors (BJTs) are presented. The circuit realizes inductance by impedance gyration using a CC-CE pair, with the parasitic capacitance between the base and emitter of the CE transistor as the load. A feedback network consisting of two parallel RC networks in series is used to produce a flat inductance versus frequency response by compensating for the pi model elements of the transistors. Using the S-parameters of NEC NE57800 transistors (f tau approximately=6 GHz), an analysis of the proposed circuit predicted an inductance of 4+or-1 nH and a resistance of less than 14 Omega up to a frequency of 2.5 GHz. The resonant frequency of the circuit was computed to be about 3.45 GHz. An integrated version of this circuit could prove to be useful for monolithic microwave integrated circuits using BJTs. >

Circuit board assembly

Abstract: A circuit board assembly for data equipment such as those having large numbers of layers and great power requirements in a small space having high computer performance, includes a multi-layer printed circuit board in laminated technology provided with voltage supply and signal carrying layers and pressure contacts at both sides connecting the multi-layer printed circuit board to further printed circuit boards. The further printed circuit boards, which are formed using micro-wiring technology, include backsides which are free of electrical components and connected to the pressure contacts and opposite sides carrying integrated electrical elements such as circuit chips forming an electrical circuit. Cooling plates are pressed against the surfaces of the circuit chips.

Mismatch sensitivity of a simultaneously latched CMOS sense amplifier

Abstract: The authors introduce a new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in dynamic RAMs (DRAMs) to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bitline load capacitance mismatch. The perturbation approach is rigorous; it avoids most approximations and ad hoc assumptions, and it introduces no free constants to be determined from simulations. The perturbation approach yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design. >