Showing papers on "Parasitic capacitance published in 1994"

Capacitance-based proximity with interference rejection apparatus and methods

Abstract: Apparatus and method for a capacitance-based proximity sensor with interference rejection. A pair of electrode arrays establish a capacitance on a touch detection pad, the capacitance varying with movement of a conductive object near the pad. The capacitance variations are measured synchronously with a reference frequency signal to thus provide a measure of the position of the object. Electrical interference is rejected by producing a reference frequency signal which is not coherent with the interference.

The use of parasitic nonlinear capacitors in class E amplifiers

Abstract: The most common class E amplifier configuration uses a single transistor with a shunt capacitor and a series resonant output filter. Until now a linear shunt capacitance has been assumed. However, to achieve operation at 900 MHz and above, it is of interest to rely solely upon the nonlinear parasitic collector-substrate capacitance of the transistor. An analytical theory for operation at 50% duty cycle and nonlinear capacitance is presented in this correspondence, and the effects on the power capability of the amplifier are discussed. >

Stray capacitances of two winding transformers: equivalent circuit, measurements, calculation and lowering

Abstract: As long as it works linearly, a two winding transformer is, from an electrostatic point of view, a three port system. Its capacitance matrix includes six independent values. Consequently, whatever its shape, introducing six capacitances in the right places of the equivalent circuit allows the user to account for the whole electrostatic behaviour of this component. With such an equivalent circuit, resonance frequencies can be computed and, reversely, the six capacitances are all deducible from measured resonance frequencies. Thus, using this circuit by hand or by software, interwinding currents of real electronic circuits can be forecasted together with parasitic resonances related to the transformer. After this global approach, a microscopic approach is adopted. A closer look at the winding layer shape and then, at the wire shape itself leads to two simple models which allow the six capacitances of the equivalent circuit to be computed by hand. Values found are approximate but, thanks to analytical expressions, two design rules leading to lower capacitance values are inferred. Measurements are presented to establish the reliability of the equivalent circuit and to evaluate the interest of the proposed designing rules. >

TFT with Reduced Parasitic Capacitance

Abstract: A thin film transistor (TFT) array in an active matrix liquid crystal display (AMLCD) including a centrally located round source electrode substantially completely surrounded by a substantially annular or circular shaped drain electrode. The geometric design of the TFT of this invention provides for a thin film transistor having a reduced parasitic capacitance and decreased photosensitivity. The TFTs of this invention are located at the intersections of gate and drain lines of an active matrix LCD array thereby increasing the size of the pixel display openings of the matrix array.

An optimized DC-to-DC converter topology for high-voltage pulse-load applications

Abstract: This paper presents the study of a high-voltage DC/DC resonant converter which has excellent behaviour to be used in applications with strong variations in output voltage and in output current, because it maintains high efficiency in these types of applications. To do so, the switching losses have been minimized by integrating all parasitic elements (leakage inductance, secondary side capacitance of the high-voltage transformer and parasitic capacitances of the power switches and diodes) into the power topology, and the conduction losses have been minimized by operating the converter in a special mode (optimum switching line) in which no reactive energy is returned from the resonant elements to the input voltage source. The type of control used (PWM phase-shifted) allows one to maintains these desirable characteristics even when the operating point suffers a very strong variation. The final power topology might be called a "full-bridge, clamped mode, LCC-type parallel resonant converter with capacitive output filter". >

Modelling iron-powder inductors at high frequencies

Abstract: A high-frequency model of iron-powder core inductors is studied. The skin and proximity effects that cause the winding parasitic resistance to increase with the operating frequency are considered. The inductor self-resonance due to the parasitic capacitances is also taken into account. The frequency response of the inductor model is compared to that of an experimentally tested iron-powder core inductor. The first self-resonant frequency is determined from the plot of the measured reactance and allows for the calculation of the parasitic capacitance. Equations for the inductor parasitic resistance are derived in a closed form. Expressions giving the AC resistance as a function of the operating frequency are given. These expressions allow for an accurate prediction of the inductor power loss over a wide frequency range. The measured and calculated values of the inductor impedance magnitude end phase, the real and imaginary parts of the inductor impedance, the inductance, and the inductor quality factor are plotted versus frequency and compared. Theoretical results were in good agreement with those experimentally measured. Therefore, it is demonstrated that the discussed equivalent circuit has a frequency response matching that of the real inductor. Moreover, the circuit model is simple, it allows for an immediate understanding of iron-powder core inductor behavior and can be easily used in computer simulations of electronic circuits. >

High frequency and high resolution capacitance measuring circuit for process tomography

Abstract: A stray-immune AC capacitance measuring circuit has been developed for electrical capacitance tomography. For this application a high excitation frequency is essential to achieve high sensitivity and fast data collection rates, and also to reduce the effect of any conductive component in parallel with the measured capacitance. A high excitation frequency has been made possible by using some novel methods: (a) a high frequency digital signal generator; (b) parameter-optimised AC amplifiers and (c) a phase-sensitive demodulator utilising CMOS switches. With a 500 kHz excitation signal the circuit has good linearity and stability, and a resolution of 0.035 fF.

Dynamic RAM and information processing system using the same

Abstract: A dynamic RAM is provided using a sense amplifier compensating for the disparities of characteristics for paired MOSFET's. With this arrangement parasitic capacitance of the bit lines can be increased to be at least 20 times the capacitance of the memory cells. Each bit line is bisected by a switch MOSFET and is disconnected thereby as needed. A plurality of sets of memory arrays are furnished, each including a switch MOSFET for interconnecting common source lines to which the sense amplifier is connected. This permits recycling of the charges of the common source lines.

Inverter circuit for use with discharge tube

Abstract: An inverter circuit for use with a discharge tube or lamp such as a cold-cathode fluorescent lamp, a hot-cathode fluorescent lamp, a mercury arc lamp, a metal halide lamp, a neon lamp or the like is provided. The secondary side circuit of a step-up transformer used in the inverter circuit is constructed as a high frequency power supply circuit and a parasitic or stray capacitance produced in the secondary side circuit of the step-up transformer is utilized as a portion or component of a resonance circuit consisting of an inductive ballast or the inductive output of a leakage flux type step-up transformer and the parasitic capacitance.

Multi-level conductor process in VLSI fabrication utilizing an air bridge

Abstract: This invention deals with the formation of the multi-level electrode metal structure and the interconnecting inter-level metal studs used in the fabrication of VLSI circuits. After the metal layers have been formed the inter-level dielectric material used in forming the structure is etched away leaving an air dielectric between the levels. The electrode metal and the inter-level metal studs are coated with a thin envelope oxide and the entire structure is covered with a passivation layer using material with a poor step coverage. The structure of this invention provides reduced parasitic capacitance, better step coverage in interconnecting layers, and improved circuit performance.

A 10-b 125-MHz CMOS digital-to-analog converter (DAC) with threshold-voltage compensated current sources

Abstract: This paper describes a 10-b high-speed COMS DAC fabricated by 0.8-/spl mu/m double-poly double-metal CMOS technology. In the DAC, a new current source called the threshold-voltage compensated current source is used in the two-stage current array to reduce the linearity error caused by inevitable current variations of the current sources. In the two-stage weighted current array, only 32 master and 32 slave unit current sources are required. Thus silicon area and stray capacitance can be reduced significantly. Experimental results show that a conversion rate of 125 MHz is achievable with differential and integral linearity errors of 0.21 LSB and 0.23 LSB, respectively. The power consumption is 150 mW for a single 5-V power supply. The rise/fall time is 3 ns and the full-scale settling time to /spl plusmn/1/2 LSB is within 8 ns. The chip area is 1.8 mm/spl times/1.0 mm. >

Methods for fabrication of thin film inductors, inductor networks, inductor/capactor filters, and integration with other passive and active devices, and the resultant devices

Abstract: The fabrication of thin film inductors on a substrate, which may include thin film resistors, thin film capacitors, and semiconductor devices. In one embodiment an inductor is fabricated initially on a substrate and then integrated with other devices subsequently formed on the substrate. In this embodiment, process steps used to fabricate such other devices utilize temperatures sufficiently low to prevent damaging or destroying the characteristics of the inductor. In another embodiment the fabrication of an inductor is achieved through photoresist masking and plating techniques. In alternative embodiments, fabrication of an inductor is achieved by sputtering, photoresist processes and etching/ion-milling techniques. A combination of various individual process steps from various embodiments are suitable for use to fabricate the individual layers to achieve a structure of this invention. The inductor fabricated in accordance with this invention is connected to other passive or active components through metal interconnections in order to improve the frequency performance of the inductor. In certain embodiments, parasitic capacitance of the inductor is significantly reduced by fabricating inductor coils on dielectric bridges. In certain embodiments, a magnetic core of ferromagnetic material is used to improve the performance of the inductor at frequencies below about 100 MHz.

Circuit for measuring the output power from an amplifier

Abstract: The object of the invention is a circuit for monitoring the power of a transmitter amplifier. In the solution according to the invention, the detected DC voltage level (Vdet) corresponding to the output power is compressed at high output levels by using as the coupling capacitance a capacitance diode (7) such that the capacitance of this component, and thereby the tightness of the coupling, diminishes as the detected voltage level increases. The invention can be employed, for example, in the power control of a mobile phone's transmitter.

Thin film inductors, inductor network and integration with other passive and active devices

Abstract: The fabrication of thin film inductors on a substrate, which may include thin film resistors, thin film capacitors, and semiconductor devices. In one embodiment an inductor is fabricated initially on a substrate and then integrated with other devices subsequently formed on the substrate. In this embodiment, process steps used to fabricate such other devices utilize temperatures sufficiently low to prevent damaging or destroying the characteristics of the inductor. In another embodiment the fabrication of an inductor is achieved through photoresist masking and plating techniques. In alternative embodiments, fabrication of an inductor is achieved by sputtering, photoresist processes and etching/ion-milling techniques. A combination of various individual process steps from various embodiments are suitable for use to fabricate the individual layers to achieve a structure of this invention. The inductor fabricated in accordance with this invention is connected to other passive or active components through metal interconnections in order to improve the frequency performance of the inductor. In certain embodiments, parasitic capacitance of the inductor is significantly reduced by fabricating inductor coils on dielectric bridges. In certain embodiments, a magnetic core of ferromagnetic material is used to improve the performance of the inductor at frequencies below about 100 MHz.

Planar GaAs Schottky diodes integrated with quartz substrate circuitry for waveguide subharmonic mixers at 215 GHz

Abstract: A novel fabrication procedure is described which integrates a GaAs active device with passive quartz microstrip circuitry to form a hybrid-substrate millimeter-wave integrated circuit structure. The procedure is used to form antiparallel-pair Schottky-barrier diodes and integrated subharmonic mixer filter circuitry at 215 GHz. A single sideband noise temperature of 2350 K and conversion loss of 10 dB has been achieved with this configuration, which is only slightly higher than the best results obtained from either whisker contacted diodes or discrete planar diode structures. Reduction of the device parasitic capacitance to levels consistent with state-of-the-art discrete planar diodes, by slight modification of the current fabrication process, is expected to bring the noise and conversion loss down by at least 2 dB, consistent with the best reported subharmonic mixers at this frequency. >

Using the hybrid series-parallel resonant converter with capacitive output filter and with PWM phase-shifted control for high-voltage applications

Abstract: This paper presents the study of a high-voltage DC-to-DC resonant power converter which has excellent behaviour to be used in applications with strong variations in the output voltage and in the output current, because it maintains high efficiency in these types of applications. To do so, the switching losses have been minimized by integrating all parasitic elements (leakage inductance, secondary side capacitance of the high-voltage transformer and parasitic capacitances of the power switches and diodes) into the power topology, and the conduction losses have been minimized by operating the power converter in a special mode (optimum switching line) in which no reactive energy is returned from the resonant elements to the input voltage source. The type of control used (PWM phase-shifted) allows one to maintain these desirable characteristics even when the operating point suffers a very strong variation. The final power topology might be called a "hybrid series-parallel resonant power converter with capacitive output filter". >

Photoelectric converting circuit having an amplification factor

Abstract: A photoelectric converting circuit having a photodiode generating a photoelectric current in accordance with the quantity of light, a first integrating circuit integrating the photoelectric current to convert it into a voltage, and a charge amplifier amplifying the change in the output voltage of the first integrating circuit. The charge amplifier is composed of a second integrating circuit and a coupling capacitance connected between the output of the first integrating circuit and the input of the second integrating circuit. The change in the output of the second integrating circuit is proportional to the ratio of the coupling capacitance to the integration capacitance of the second integrating circuit. This makes it possible to improve the sensitivity of the photoelectric converting circuit without reducing the value of the integration capacitance of the first integrating circuit.

Input stage improvement for current feedback amplifiers

Abstract: A current feedback amplifier having circuitry in its input stage for matching the error current created due to a parasitic capacitance (C IN ) on the negative, or inverting input terminal (V IN- ). Additional circuitry in the input stage subtracts the matching current from the error current created by C IN to cancel the error current due to C IN and thus eliminate the peaking of gain at high frequencies caused by C IN . In addition to cancellation of C IN errors, the subtraction process in the input stage enables cancellation of error current resulting from bias current common mode rejection (ICMR) as well as component dissimilarities created during processing.

Semiconductor memory device with bit line and select line arrangement maintaining parasitic capacitance in equilibrium

Abstract: A semiconductor memory device in which sensing of the memory information stored in a memory cell can be carried out stably, and reliably by equilibrating a parasitic capacitance existing between a select line and its adjacent bit line pair. Each Y select line YS is arranged at a position where it uniformly spans over both members of a bit line pair which extend straight in parallel to each other without the twist part TW within an area of four bit line pairs (eight bit lines or auxiliary bit lines) that are simultaneously sensed. Within an area of the first set of bit line pairs (BL0,BL0-)-(BL3,BL3-), in addition to the bit line pair (BL1,BL1-), the line pairs (BL0,BL0-) and (BL2,BL2-) with the twist part TW are substantially capacitance-coupled with the Y select line YS0. In these bit line pairs, the parasitic capacitance for the Y select line YS0 is at equilibrium between a bit line and an auxiliary bit line.

Planar millimeter-wave microstrip lumped elements using micro-machining techniques

Abstract: Planar millimeter-wave microstrip inductors and capacitors have been fabricated on high-resistivity silicon substrates using micro-machining techniques. The spiral inductors and interdigitated capacitors are suspended on a thin dielectric membrane to reduce the parasitic capacitance to ground. The resonant frequencies of a 1.2 nH and a 1.7 nH inductor fabricated on a high-resistivity silicon substrate and on a small dielectric membrane, have been increased from 22 GHz and 17 GHz to 73 GHz and 54 GHz, respectively. The planar micro-machined elements are compatible with the via-hole technology process in GaAs and InP MMIC, and can be used as true inductors and capacitors up to 50-60 GHz. The technique can be also applied to lumped elements in coplanar-waveguide transmission lines. >

Design of thin-film fully-depleted SOI CMOS analog circuits significantly outperforming bulk implementations

Abstract: Although the reduction of parasitic capacitance and the feasibility of diffusion resistors and capacitors free of junction effects have long been recognized as advantages for the realization of analog circuits on SOI substrates, few SOI analog circuits have been reported mainly because the kink effect severely degrades the output characteristics of thick-film SOI MOSFETs and thereby the performances of analog circuits. Operational amplifier solutions such as the use of body contacts, twin-gate devices or gain-boosting have been proposed but offer little improvement over bulk CMOS counterparts, with the exception of the resistance to elevated temperatures. In the present paper we propose new design models and techniques which, by exploiting the smaller subthreshold swing and body factor of thin-film fully-depleted (FD) SOI MOSFETs, could provide a major breakthrough in order to boost the performances of SOI CMOS analog circuits substantially over bulk implementations, especially in the field of low-voltage low-power applications.

Method and apparatus to measure capacitance

Abstract: A capacitance measuring device incorporates the integrating analog-digital converter circuit of a handheld meter. The capacitance measuring device charges an unknown capacitance with a constant current until the voltage across the unknown capacitor reaches a predetermined voltage. At the same time, a reference voltage is applied to the input lead of an integrating circuit of the integrating analog-digital converter such that a corresponding proportional charge is stored in the feedback capacitor of the integrating circuit. The negative of the reference voltage is then applied to the integrating circuit so that charge is removed from the feedback capacitor at the same rate as the feedback capacitor was charged. A counter is used to determine the number of clock pulses it took to completely discharge the feedback capacitor and hence a reading of the unknown capacitance can be determined from the equation CX =ICHARGE *T2 /VTRIP.

A high inductance kHz resonator with a quality factor larger than 106

Abstract: Electrical LC resonators with superconducting coils of ≊3.5 H inductance, operating in the frequency range 250–1500 Hz with quality factors up to Q≊1.6×106 are presented here. The coil has a reduced, <100 pF, stray capacitance and is housed in a superconducting case. Measurements are made with a low coupling SQUID readout. Some possible applications of the device are briefly discussed.

Dynamic random access memory device having one-transistor one-capacitor type memory cells coupled between bit lines paired with each other

Abstract: A dynamic random access memory device has a plurality of one-transistor one-capacitor type memory cells each coupled between a first bit line and a second bit line paired with the first bit line, and parasitic capacitance coupled with the first bit line is approximately equal to a parasitic capacitance coupled with the second bit line so that a large potential difference takes place between the first and second bit lines when the storage capacitor is coupled with the first and second bit lines precharged to an intermediate voltage level.

Variable capacitor with very fine resolution

Abstract: The resolution ΔC of a binary capacitance ladder having a plurality of N branches is precisely determined by appropriately selecting the value of a fixed capacitor in each branch relative to the parasitic capacitance of a corresponding series-connected switch. The capacitance of each respective branch varies by 2 n-1 ΔC, where n is the number of the branch, adjacent branches being numbered sequentially. The total capacitance is variable between C Total and C Total -(2 N -1)ΔC in steps of ΔC, where C Total is the sum of the capacitances in the ladder with all switches closed, and C Total -(2 N -1)ΔC is the capacitance of the ladder with all switches open. For any particular branch of the ladder, the switch capacitance may be further controlled by adding a fixed capacitance in parallel with the respective switch. Such a variable capacitance is useful as a tuning capacitor in an electrodeless HID lamp ballast.

Semiconductor device and its manufacture

Abstract: PROBLEM TO BE SOLVED: To provide a resistance element which can reduce the amplification factor variations of an amplifier circuit incorporating a bipolar transistor and the parasitic capacitance of the circuit in a semiconductor device composed of the bipolar transistor and resistance element SOLUTION: In the method for manufacturing a semiconductor device, a bipolar transistor is formed on a silicon substrate 10 Then, after an insulating film 42 is formed on the bipolar transistor, a contact hole is formed and wiring plugs 44 and wiring 46 are formed of metallic films having high melting points In addition, the characteristics of the transistor are measured with a monitor and the resistance value at which the output of the semiconductor device becomes a prescribed current value and a prescribed voltage value is found Thereafter, a polysilicon film containing impurities is formed on the insulating film 42 by controlling the impurity concentration and thickness of the film and, in addition, a resistance value 24 which becomes the resistance value is formed through a patterning process

High-frequency choke circuit

Abstract: A high-frequency choke circuit comprises a dielectric layer covered with grounding conductors, a lead line of high-impedance and at least one capacitance land formed within the dielectric layer, and at least one through-hole connecting the lead line and the capacitance land. The capacitance lands are disposed closer to the grounding conductors, resulting in large capacitances with small areas. The capacitance lands are formed on a layer distant from the layer on which the lead line is formed. Therefore, unnecessary electromagnetic coupling with other circuits formed on the same layer as the lead line can be reduced. The grounding conductors cover both surfaces of the dielectric layers that incorporate the capacitance lands and the lead line to thereby shield the circuit formed in the dielectric layers electromagnetically from outside.

Field-effect transistor

Abstract: PURPOSE:To provide a FET capable of reducing parasitic capacitance between a gate and a drain while having a single gate FET characteristic. CONSTITUTION:In a field-effect transistor, an active layer is provided in a surface side of a semiconductor substrate 1, and a gate electrode 5 and a gate electrode 5 are interposed between a source electrode 6 and a drain electrode 7. which are respectively provided on the active layer. A shield wire 9 is provided between the gate electrode 5 and the drain electrode 7.

A 60 joule, 600 kv, 500 ps risetime, 60 ns pulse width marx generator

Abstract: The experimental and computer modelling of the performance of a 24-stage coaxial line Marx generator are presented. Internal inductance, stray capacitance, coupling capacitance between the stages and switch characteristic are considered. The detailed geometry of each stage and of the total system is included in the computer simulation. The UV pre-ionized spark gaps forming the switches in the system are characterized by the spark overvoltage. The transmission line effects are also observed. The output characteristics are given at different overvoltages.

Laminate type LC composite device having a micro coil

Abstract: A laminate type LC composite device has a coil connected in series between an input electrode and an output electrode, and a capacitor connected in parallel between the input electrode and the output electrode. Further, a micro coil is connected to the coil in series. The coil has an inductance of L and a stray capacitance of C, and the micro coil has an inductance of L' and a stray capacitance of C'. The inductances L and L', and the stray capacitances C and C' fulfill the conditions: LC>L'C', to thereby increase the high-frequency characteristics and the insertion loss in a high frequency area of the LC composite device.