Showing papers on "Parasitic capacitance published in 1998"

On-chip spiral inductors with patterned ground shields for Si-based RF ICs

Abstract: This paper presents a patterned ground shield inserted between an on-chip spiral inductor and silicon substrate. The patterned ground shield can be realized in standard silicon technologies without additional processing steps. The impacts of shield resistance and pattern on inductance, parasitic resistances and capacitances, and quality factor are studied extensively. Experimental results show that a polysilicon patterned ground shield achieves the most improvement. At 1-2 GHz, the addition of the shield increases the inductor quality factor up to 33% and reduces the substrate coupling between two adjacent inductors by as much as 25 dB. We also demonstrate that the quality factor of a 2-GHz LC tank can be nearly doubled with a shielded inductor.

An improved family of ZVS-PWM active-clamping DC-to-DC converters

Abstract: A new family of DC-to-DC converters featuring clamping action, PWM modulation and soft-switching (ZVS) in both active and passive switches, is proposed to overcome the limitations of clamped mode DC-to-DC converters. The new family of converters is generated and the new circuits are presented. As the resonant circuits absorb all parasitic reactances, including transistor output capacitance and diode junction capacitance, these converters are suitable for high-frequency operation. Principle of operation of the boost converter, theoretical analysis, simulation and experimental results are presented, taken from a laboratory prototype rated at 1600 W, input voltage of 300 V, output voltage of 400 V, and operating at 100 kHz. The measured efficiency at full load was 98%.

Power factor correction method and apparatus

Abstract: A method and apparatus for controlling a boost converter, which offers improved power factor correction by compensating for the distorting effects of parasitic capacitance and parasitic oscillations. By precise adjustments to the closing time of the boost switch, the effects of parasitic capacitance can be reduced or eliminated. A zero current detector capable of detecting both forward and reverse zero current points facilitates the compensation. The method and circuit of the present invention are well-suited to integration with an inexpensive digital controller such as a microprocessor, and a method of dithering to enhance the time resolution of clocked digital circuits is presented.

Porous silicon oxycarbide integrated circuit insulator

Abstract: An integrated circuit includes at least one porous silicon oxycarbide (SiOC) insulator (140, 305), which provides low dielectric constant (e.g., eR < 2) for minimizing parasitic capacitance. The insulator provides IC isolation, such as between circuit elements (115), between interconnection lines (300, 315), between circuit elements (115) and interconnection lines (300, 315), or as a passivation layer (320) overlying both circuit elements and interconnection lines.

Direct drive backlight system

Abstract: A power conversion circuit drives a cold cathode fluorescent lamp (CCFL) while requiring minimal number of external components. The circuit includes a controller, a direct drive network responsive to control inputs from the controller and coupled to receive a power signal, and a secondary network coupled to the CCFL. The direct drive network is low Q circuit comprising a plurality of switching transistors and a primary winding of a transformer such that an impedance of the direct drive network consists essentially of an inductance of the primary winding and capacitance of the direct drive network consists essentially of parasitic capacitance reflected from the secondary winding. The Q of the direct drive network is less than about 0.5 so that a square wave voltage signal is provided across the primary winding of the transformer. However, the inductance of the transformer is sufficiently high such that the voltage across a secondary winding of the transformer is sinusoidal. The secondary network comprises the secondary winding of the transformer coupled to the CCFL through a connector to provide a sinusoidal current to the CCFL. The controller controls the current passing through the CCFL by pulse width modulating the control inputs to the direct drive network.

Surface micromachined solenoid inductors for high frequency applications

Abstract: As operation frequencies and performance requirements of wireless devices increase, the resultant demands on the performance of passive components also increase. Miniaturization of inductive components for high frequency has been a key research area to address this issue; however, in general, miniaturized integrated inductors can suffer from low Q factors and/or self-resonant frequencies when compared to their discrete counterparts. In this research, a modified geometry of a solenoid type inductor using a surface micromachining technique is proposed. This inductor has an air core and an electroplated copper coil to reduce the series resistance, and its low temperature process is suitable for various packaging applications. An important feature of the proposed inductor geometry is the introduction of an air gap between the substrate and the conductor coil in order to reduce the effects of the substrate dielectric constant. This air gap can be realized using a polyimide sacrificial layer and a surface micromachining technique. Therefore, the resulting inductor can have less substrate-dependent magnetic properties, less stray capacitance, and higher Q-factor. The measurement result shows that this inductor has high Q-factor and stable inductance over a wide range of operating frequency. Also, various effects of geometrical factors have been investigated. Various inductors with the inductance varying from 1 to 20 nH and maximum Q-factor from 7 to 60 have been fabricated and measured.

Apparatus and method for starting a fluorescent lamp

Abstract: A power conversion circuit drives a cold cathode fluorescent lamp (CCFL) while requiring minimal number of external components. The circuit includes a controller, a direct drive network responsive to control inputs from the controller and coupled to receive a power signal, and a secondary network coupled to the CCFL. The direct drive network is low Q circuit comprising a plurality of switching transistors and a primary winding of a transformer such that an impedance of the direct drive network consists essentially of an inductance of the primary winding and capacitance of the direct drive network consists essentially of parasitic capacitance reflected from the secondary winding. The Q of the direct drive network is less than about 0.5 so that a square wave voltage signal is provided across the primary winding of the transformer. However, the inductance of the transformer is sufficiently high such that the voltage across a secondary winding of the transformer is sinusoidal. The secondary network comprises the secondary winding of the transformer coupled to the CCFL through a connector to provide a sinusoidal current to the CCFL. The controller controls the current passing through the CCFL by pulse width modulating the control inputs to the direct drive network.

Investigation of interconnect capacitance characterization using charge-based capacitance measurement (CBCM) technique and three-dimensional simulation

Abstract: This paper examines the recently introduced charge-based capacitance measurement (CBCM) technique through use of a three-dimensional (3-D) interconnect simulator. This method can be used in conjunction with simulation at early process development stages to provide designers with accurate parasitic interconnect capacitances. Metal to substrate, interwire, and interlayer capacitances are each discussed and overall close agreement is found between CBCM and 3-D simulation. Full process interconnect characterization is one possible application of this new compact, high-resolution test structure.

A model of artefacts produced by stray capacitance during whole body or segmental bioimpedance spectroscopy

Abstract: We have developed a novel model for the simulation of artefacts which are produced by stray capacitance during bioimpedance spectroscopy. We focused on whole body and segmental measurements in the frequency range 5-1000 kHz. The current source was assumed to by asymmetric with respect to ground as is the case for many commercial devices. We considered the following stray pathways: 1, cable capacitance; 2, capacitance between neighbouring electrode leads; 3. capacitance between different body segments and earth; 4, capacitance between signal ground of the device and earth. According to our results the pathways 3 and 4 cause a significant spurious dispersion in the measured impedance spectra at frequencies > 500 kHz. During segmental measurements the spectra have been found to be sensitive to an interchange of the electrode cable pairs. The sensitivity was also observed in vivo and is due to asymmetry of the potential distribution along the segment with respect to earth. In contrast to previously published approaches, our model renders possible the simulation of this effect. However, it is unable to fully explain the deviations of in vivo measured impedance spectra from a single Cole circle. We postulate that the remaining deviations are due to a physiologically caused superposition of two dispersions from two different tissues.

A 156-Mb/s CMOS optical receiver for burst-mode transmission

Abstract: In a point-to-multipoint fiber-optic subscriber system using TDMA (time division multiple access), the receiver should be able to handle burst-data packets with different amplitudes, Moreover, high-bit-rate operation is desired for multimedia communications. The operational speed is mainly restricted by the input parasitic capacitance of the preamplifier. Reducing the input impedance of the preamplifier widens its frequency bandwidth, and it makes high-speed operation possible. A multistaged preamplifier using feedforward phase compensation technique has been devised for small input impedance with stable operation at high frequency. Multistaged feedforward bias control is used for quick response to burst data, and the time constant is also reduced for high-speed operation. Using these design techniques, an optical receiver IC was fabricated using standard 0.5-/spl mu/m CMOS technology. The instantaneous response receiver has high sensitivity of -35.6 dBm, a wide dynamic range of more than 26 dB for burst-mode optical input at 156 Mb/s, and requires no external adjustment. The use of standard CMOS technology and the freedom from external adjustment make it possible to build an inexpensive receiver module.

Multilevel interconnection structure having an air gap between interconnects

Abstract: A semiconductor device has an air-gap/multi-level interconnection structure. The interconnects are insulated from one another by an air gap in the same layer, and by an interlevel dielectric film between layers and from a semiconductor substrate. A high-speed semiconductor device is obtained due to a lower parasitic capacitance.

Accurate Characteristic Impedance Measurement on Silicon

Abstract: This paper presents a new method that accurately determines the characteristic impedance of planar transmission lines printed on lossy dielectrics even when contact-pad capacitance and conductance are large. We demonstrate the method on a coplanar waveguide fabricated on fused silica and a microstrip line fabricated on a highly conductive silicon substrate.

Substrate interconnect for power distribution on integrated circuits

Abstract: A backside interconnect structure is used to deliver power through the substrate to the front side of an integrated circuit. One or more power planes are formed on the backside of the substrate and coupled to power nodes on the front side by deep vias in the substrate. In a specific embodiment of the invention, power planes are coupled through the substrate to front side metal lines, well taps and external connection points. Placing power planes on the opposite side of the substrate from the signal interconnects allows the use of low dielectric constant materials between signal lines, while using high dielectric constant materials between power planes thus increasing decoupling capacitance without increasing parasitic capacitance between signal lines.

Low capacitance interconnection

Abstract: A semiconductor device having reduced parasitic capacitance and, consequentially increased integrated circuit speed, is achieved by removing sections of dielectric interlayers which do not support conductive patterns, as by anisotropic etching, to form air gaps which can remain or are filled in with a dielectric material having a low dielectric constant. In another embodiment, a conformal dielectric coating is deposited, having a low dielectric constant.

Method and apparatus for providing analog and digitally controlled capacitances for synthesizing high-frequency signals for wireless communications

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, a digital control signal is disclosed to control the overall capacitance for the discretely variable capacitance circuit, and a variable control signal is disclosed to control an overall capacitance for the continuously variable capacitance circuit. In addition, the output frequency may be varied by adjusting either the digital control word or the variable control word.

Method and apparatus for generating a variable capacitance for synthesizing high-frequency signals for wireless communications

Abstract: A method and apparatus for synthesizing high-frequency signals, such as wireless communication signals, includes a phase-locked loop (PLL) frequency synthesizer with a variable capacitance voltage controlled oscillator (VCO) that has a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance to compensate for capacitor and inductor tolerances and to adjust the output frequency to be near the desired frequency output. The continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance to focus the output frequency to match precisely the desired frequency output. The continuously variable capacitance may be formed by using a plurality of separate capacitance circuits. The individual capacitance circuits may include two capacitors coupled to a variable resistance element. The variable resistance element may be a transistor controlled by an analog control voltage. The total capacitance of the continuously variable capacitance may be substantially linear with respect to the phase of the VCO output while the individual capacitance circuits exhibit nonlinear behavior.

Active capacitance multipliers using current conveyors

Abstract: One of the most limiting problems in the design of integrated circuits is constituted by the realization of high valued capacitors, who have the heavy drawback of high occupation of silicon area. Moreover, in some sensor applications, it can be useful to deal with capacitance values higher than those normally given by capacitive sensors. In these cases, the use of capacitance multipliers can be very important. In this paper, we propose a novel principle of simple capacitance multipliers, by which it is possible to obtain higher capacitive values. Two solutions, the first using one CCII- with current gain and the second using two conventional CCIIs, are presented and analyzed. The effects of CCII non-idealities are also evaluated and discussed. Finally, SPICE simulations, which are in a close agreement with the analytical calculations, are also reported.

High-linearity, low-spread variable capacitance array

Abstract: The invention provides a unique apparatus and method which varies the capacitance coupled to a circuit. In one embodiment, the variable capacitance comprises a unique variable capacitance array (402) with multiple capacitance modules (508, 540 and 550) which can be selectively enabled. Each capacitance module has a capacitive value (510, 542, 544, 552 and 556) and a corresponding parasitic capacitance. The invention provides high linearity, low spread, improves the response to power fluctuations by maintaining a consistent relationship between the capacitive value (510, 542, 544, 552 and 556) and the parasitic capacitance in each capacitance module (508, 540 and 550). For example, the invention can be used with devices to provide a linear variation of capacitance. In addition, the invention can be used to calibrate a wide range of devices.

Improved 240-GHz subharmonically pumped planar Schottky diode mixers for space-borne applications

Abstract: Low-noise broad intermediate frequency (IF) band 240-GHz subharmonically pumped planar Schottky diode mixers for space-borne radiometers have been developed and characterized. The planar GaAs Schottky diodes are fully integrated with the RF/IF filter circuitry via the quartz-substrate upside-down integrated device (QUID) process resulting in a robust and easily handled package. A best double-sideband-mixer noise temperature of 490 K was achieved with 3 mW of local-oscillator power at 2-GHz IF. Over an IF band of 1.5-10 GHz, the noise temperature is below 1000 K. This state-of-the-art performance is attributed to lower parasitic capacitance devices and a low-loss waveguide circuit. Device fabrication technology and the resulting RF mixer performance obtained in the 200-250-GHz frequency range will be described.

Universal MEMS platforms for passive RF components: suspended inductors and variable capacitors

Abstract: We propose a universal MEMS technology platform for fabricating integrable passive components for radio frequency (RF) integrated circuits. This platform is based on a novel surface-micromachined Micro-Elevator by Self-Assembly (MESA) technique. Both high-Q inductors and variable capacitors can be realized by the MESA technology. A surface-micromachined spiral inductor that is raised by 250 /spl mu/m above the Si substrate has been experimentally demonstrated. The suspended inductor has less parasitic capacitance and substrate loss, and higher quality (Q) value and resonant frequency. The inductance of a 12.5-turn inductor is measured to be 24 nH. The results show that the self-assembled passive RF elements are suitable for monolithic integration.

Method and apparatus for a lateral flux capacitor

Abstract: Linear integrated circuit capacitors having greater capacitance per unit area by using lateral flux. One embodiment comprises a two metal layer capacitor wherein each metal layer is comprised of two capacitor conductive components. The capacitor conductive components are cross-coupled so that the total capacitance is the sum of the vertical flux between the metal layers, and the lateral flux along the edges between the two capacitor conductive components in each of the metal layers. The lateral flux between the capacitor conductive components in a single metal layer increases the capacitance per unit area and decreases the bottom-plate parasitic capacitance. Increasing the length of the common edge formed by capacitor conductive components in a metal layer increases the capacitance per unit area. In one lateral flux capacitor, each metal layer is comprised of a plurality of rows, alternate rows are coupled together such that lateral flux is generated between each of the rows. The rows are also cross-coupled with rows in adjacent metal layers to provide vertical flux. Fractal shapes can be used to maximize the length of the perimeter of adjacent capacitor conductive components in a single metal layer. The Koch Islands and Minkowski Sausage families of fractals are particularly well suited for generating capacitor conductive component perimeter shapes. These fractals are generated by selecting an initiator shape and repeatedly applying a generator. The fractal shapes are generated by a computer program based upon user input parameters.

Fabrication method of inductor devices using a substrate conversion technique

Abstract: A fabrication method of high performance integrated inductor devices using a substrate conversion technique is disclosed. By employing the trench-shaped porous silicon with high insulating property, the lossy characteristic of the silicon substrate is essentially to minimize. Also, by employing the conductive doped layer interposed between the porous silicon layer and the silicon substrate, the parasitic capacitance between metal lines and the silicon substrate is remarkably decreased. The present invention allows fabrication of high performance integrated inductors having high quality factor. Also, this invention prevents mutual-coupling between the silicon substrate and metal lines. As a result, integrated inductor devices according to this invention is readily adaptable for use in radio frequency integrated circuit (RF IC).

Methods and apparatus for extracting parasitic capacitance values from a physical design of an integrated circuit

Abstract: Computer-implemented methods and apparatus for extracting and computing parasitic capacitance values and capacitances respectively, from a physical design of an integrated circuit are described. In one embodiment, the physical design comprises a plurality of layered conductors which are disposed within a first dielectric material. At least one conductor of the plurality of conductors is identified, and for the identified conductor, the first dielectric material is replaced for calculational purposes with a second (fictitious) dielectric material having a dielectric constant which is higher than the dielectric constant of the replaced dielectric material. In general, the second dielectric may have a different dielectric constant for each identified layer or elevation. Parasitic capacitance values are then computed for the integrated circuit. In a preferred embodiment, spaced-apart conductors at a common substrate elevation are identified, and a distance between the conductors is determined. If the determined distance exceeds a predetermined distance value, the first dielectric material is replaced with the second dielectric material. Such provides a basis for extracting parasitic capacitance values and computing one or more parasitic capacitances which more accurately represents the effect of the presence of fill structures within the physical integrated circuit.

Shielded integrated circuit capacitor

Abstract: An integrated circuit (IC) capacitor offers reduced sensitivity to parasitic capacitance, reduced-size, and increased noise immunity, such as for use in digital-to-analog converters (DACs), analog-to-digital converters (ADCs), switched-capacitor filters, and other IC circuits. The capacitor includes a first polysilicon layer, a superjacent second polysilicon layer separated from the first polysilicon layer by an insulator, and an overlying metal layer separated from the second polysilicon layer by an insulator. The metal layer provides a shield that is connected to a known voltage, or to the first polysilicon layer. When connected to the first polysilicon layer, the overlying metal layer also provides additional parallel capacitance, thereby reducing the integrated circuit area of the capacitor. In one example, the overlying metal layer is a second metal layer that is also used, together with a first metal layer, for interconnecting IC components.

Method and apparatus for eliminating floating voltage nodes within a discreetly variable capacitance used for synthesizing high-frequency signals for wireless communications

Abstract: A method and apparatus for synthesizing high-frequency signals is disclosed that overcomes integration problem associated with prior implementations while meeting demanding phase noise and other impurity requirements. In one embodiment, a phase-locked loop (PLL) frequency synthesizer is disclosed having a voltage controlled oscillator (VCO) with a variable capacitance that includes a discretely variable capacitance in conjunction with a continuously variable capacitance. The discretely variable capacitance may provide coarse tuning adjustment of the variable capacitance, and the continuously variable capacitance may provide a fine tuning adjustment of the variable capacitance. In a further detail, a capacitor circuit is disclosed for the discretely variable capacitance that includes a transistor that selectively couples a capacitor between a signal node and ground and a means for coupling a voltage node between the capacitor and the transistor to the signal node when the transistor is in an “off” state. The means for coupling may be a second transistor.

Human body capacitance: static or dynamic concept? [ESD]

Abstract: A standing human body insulated from ground by footwear and/or floor covering is in principle an insulated conductor and has, as such, a capacitance, i.e. the ability to store a charge and possibly discharge the stored energy in a spark discharge. In the human body, the human body capacitance (HBC) is traditionally chosen as 100 pF. However, a simple geometric model seems to suggest considerably higher values. A series of experiments, where the capacitance of standing persons were determined for various combinations of footwear and floor coverings, gave values in the order of 100-150 pF when the capacitance was determined by an AC-bridge measurement, but 200-400 pF when the traditional static charge-sharing method was used. Further experiments indicate that the two methods give the same result when the electric flux is well located in a dielectric other than air, but that the static method leads to higher values when a substantial part of the flux extends itself through badly defined stray fields. Since the concept of human body capacitance is normally used in a static (electric) context, it is suggested that the HBC be determined by a static method. No theoretical explanation of the observed differences is presently at hand.

SOI CMOS with high-performance passive components for analog, RF, and mixed signal design

Abstract: Summary form only given. Peregrine Semiconductor's UTSi/sup R/ silicon-on-sapphire (SOS) CMOS process is unique because it has a fully insulating substrate. This enables the design of higher performance resistors, capacitors, and inductors. The UTSi process consists of a thin (100 nm) "improved" silicon epitaxial layer on single crystal sapphire with dual polysilicon capacitors and three layers of Al metallization. All processing is standard CMOS processing for high manufacturability and reliability. The UTSi technology takes advantage of the sapphire substrate to improve resistor and inductor characteristics for high-performance analog and RF applications. Resistors with low parasitic capacitance, low TCR, and low voltage coefficients simplify the design of analog circuits. Highly linear double-poly capacitors also enable higher performance analog and RF design. The presence of high-Q inductors and capacitors and excellent isolation of the insulating substrate allow fully integrated MMICs to be designed in UTSi technology. These characteristics make UTSi an ideal technology for analog, RF integration, and mixed-signal products.

A new technique for high frequency characterization of capacitors

Abstract: To improve the accuracy for high frequency characterization of capacitors with very low inductance values, a technique is developed. The first part of the technique requires a standard calibration for a network analyzer. Then s-parameter measurements for test fixtures and adapters are measured. A high frequency circuit model for every connector or test fixture from the calibrated port to the device under test (DUT) is then de-embedded one at a time, using the measured data as a reference and each time adding in the previously de-embedded circuit model. The difference between the measured data and the simulated data is forced to be less than 1%. This stringent requirement is necessary for obtaining the high accuracy equivalent series inductance (ESL) and resistance (ESR). The requirement also guarantees the accuracy of high frequency parasitic capacitance and resistance of a capacitor. After the high frequency circuit models for all test fixtures and adapters are found, s-parameter measurements for a capacitor mounted on a test fixture with an adapter are measured. When the circuit models for the test fixture and adapter are put together and the whole system is matched to the measured s-parameter data for the whole system, the circuit model of a capacitor has been found. In this paper, two new capacitor models and several discontinuity models are also reported. The new capacitor models are valid for the entire frequency range. The discontinuity models are fully consistent with the real physical structure of test fixtures. Different capacitors from various suppliers are characterized and the high frequency circuit models are also provided.

Capacitance detecting circuit

Abstract: A capacitance detecting circuit which can ensure flexibility in application without restriction imposed by a capacitance arrangement such as a single capacitance, differential capacitance, differential capacitance electrostatic servo and like arrangements, to a great advantage includes an operational amplifier having an inverting input terminal and an output terminal between which a feedback capacitance component is connected, a capacitance sensor having an electrostatic capacitance subjected to change under action of an external force, a switch for electrically charging the capacitance component of the capacitance sensor by connecting a charge/discharge terminal of the capacitance component to a reference voltage at a first clock timing for discharging the feedback capacitance component and switching the charge/discharge terminal to the feedback capacitance component at a second clock timing to transfer electric charge, and a sample-and-hold circuit for converting the transferred electric charge to the sensor output voltage.

MOS sample and hold circuit

Abstract: A MOS track-and-hold circuit incorporating cancellation of error due to switch feedthrough is described. To eliminate the channel charge feedthrough due to oxide capacitance, a switched capacitor source (22) is connected to be charged to a voltage V1 during the "hold" phase and between the input node (12) and the switch gate (17) to provide a voltage V1-Vin during the "track" phase. A dummy transistor (26) biased in an "off" condition has its drain connected to the holding capacitor (15) and its gate switched between ground and the output terminal (Vout which tracks Vin) to also cancel the feedthrough from the gate-drain overlap capacitance and any gate-drain parasitic capacitance.