Showing papers on "Parasitic capacitance published in 2006"

Power semiconductor devices and methods of manufacture

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

Abstract: This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.

Detection of and compensation for stray capacitance in capacitive touch sensors

Abstract: The present invention provides systems and methods for detecting stray capacitance in capacitive touch sensors. The existence of stray capacitance can lead to errors in touch detection and touch position determination. Such errors can be avoided or corrected when the stray capacitance is detected. Detecting stray capacitance includes analyzing signals for features characteristic of stray capacitance noise events. Such features can include spatial features such as the location of a test touch position determined from signals caused by stray capacitance, as well as temporal features such as the rate of change of the detected signals.

High-Power Density Design of a Soft-Switching High-Power Bidirectional DC-DC Converter

Abstract: A typical non-isolated bi-directional dc-dc converter technology is to combine a buck converter and a boost converter in a half-bridge configuration. In order to have high-power density, the converter can be designed to operate in discontinuous conducting mode (DCM) such that the passive inductor can be minimized. The DCM associated current ripple can be alleviated by multiphase interleaved operation. However DCM operation tends to increase turn-off loss because of a high peak current and its associated parasitic ringing due to the oscillation between the inductor and the device output capacitance. Thus the efficiency is suffered with the conventional DCM operation. Although to reduce the turn-off loss, a lossless capacitor snubber can be added across the switch, the energy stored in the capacitor needs to be discharged before device is turned on in order to realize zero-voltage switching. This paper adopts a gate signal complimentary control scheme to turn on the non-active switch and divert the current into the anti-paralleled diode of the active switch so that the main switch can turn on under zero-voltage condition. Thus both soft switching turn-on and turn-off are achieved. This diverted current also eliminates the parasitic ringing in inductor current. For capacitor value selection, there is a trade-off between turn-on and turn-off losses. This paper suggests the optimization of capacitance selection through a series of hardware experiments to ensure the overall power loss minimization under complimentary DCM operating condition. A 100kW hardware prototype is constructed and tested. The experimental results are provided to verify the proposed design approach.

Design Considerations for Very High Frequency dc-dc Converters

Abstract: This document describes several aspects relating to the design of dc-dc converters operating at frequencies in the VHF range (30–300 MHz). Design considerations are treated in the context of a dc-dc converter operating at a switching frequency of 100 MHz. Gate drive, rectifier and control designs are explored in detail, and experimental measurements of the complete converter are presented that verify the design approach. The gate drive, a self-oscillating multi-resonant circuit, dramatically reduces the gating power while ensuring fast on-off transitions of the semiconductor switch. The rectifier is a resonant topology that absorbs diode parasitic capacitance and is designed to appear resistive at the switching frequency. The small sizes of the energy storage elements (inductors and capacitors) in this circuit permit rapid start-up and shut-down and a correspondingly high control bandwidth. These characteristics are exploited in a high bandwidth hysteretic control scheme that modulates the converter on and off at frequencies as high as 200 kHz.

Methods and systems for detecting a capacitance using switched charge transfer techniques

Abstract: Methods, systems and devices are described for detecting a measurable capacitance using charge transfer techniques. According to various embodiments, a charge transfer process is performed for two or more times. During the charge transfer process, a pre-determined voltage is applied to the measurable capacitance, and the measurable capacitance is then allowed to share charge with a filter capacitance through a passive impedance that remains coupled to both the measurable capacitance and to the filter capacitance throughout the charge transfer process. The value of the measurable capacitance can then be determined as a function of a representation of a charge on the filter capacitance and the number of times that the charge transfer process was performed. Such a detection scheme may be readily implemented using conventional components, and can be particularly useful in sensing the position of a finger, stylus or other object with respect to an input sensor.

Parasitic capacitance cancellation in filter inductors

Abstract: This paper introduces a technique for improving the high-frequency performance of filter inductors and common-mode chokes by cancelling out the effects of parasitic capacitance. This technique uses additional passive components to inject a compensation current that cancels the parasitic current, thereby improving high-frequency filtering performance. Two implementation approaches for this technique are introduced. The first implementation achieves cancellation using an additional small winding on the filter inductor and a small capacitor. This approach is effective where very high coupling of the windings can be achieved or where only moderate performance improvements are required. The second implementation utilizes a small radio frequency transformer in parallel with the filter inductor to inject cancellation currents from the compensation capacitor. This technique requires an additional component (the transformer), but can provide a high degree of cancellation. Experimental results confirm the theory in both implementations.

Nanoscale capacitance imaging with attofarad resolution using ac current sensing atomic force microscopy.

Abstract: Nanoscale capacitance imaging with attofarad resolution (∼1 aF) of a nano-structured oxide thin film, using ac current sensing atomic force microscopy, is reported. Capacitance images are shown to follow the topographic profile of the oxide closely, with nanometre vertical resolution. A comparison between experimental data and theoretical models shows that the capacitance variations observed in the measurements can be mainly associated with the capacitance probed by the tip apex and not with positional changes of stray capacitance contributions. Capacitance versus distance measurements further support this conclusion. The application of this technique to the characterization of samples with non-voltage-dependent capacitance, such as very thin dielectric films, self-assembled monolayers and biological membranes, can provide new insight into the dielectric properties at the nanoscale.

Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate–Source/Drain Underlap

Abstract: Parasitic gate-source/drain (G-S/D) fringe capacitance in nonclassical nanoscale CMOS devices, e.g., double-gate (DG) MOSFETs, is shown, using two-dimensional numerical simulations, to be very significant, gate bias-dependent, and substantially reduced by a well-designed G-S/D underlap. Analytical modeling of the outer and inner components of the fringe capacitance is developed and verified by the numerical simulations; a BOX-fringe component is modeled for single-gate fully depleted silicon-on-insulator MOSFETs. With the new modeling implemented in UFDG, our process/physics-based generic compact model for DG MOSFETs, UFDG/Spice3 shows how nanoscale DG CMOS speed is severely affected by the fringe capacitance and how this effect can be moderated by an optimal underlap, which yields a good tradeoff between the parasitic capacitance and the S/D resistance

Novel nanotube-on-insulator (NOI) approach toward single-walled carbon nanotube devices.

Abstract: We present a novel nanotube-on-insulator (NOI) approach for producing high-yield nanotube devices based on aligned single-walled carbon nanotubes. First, we managed to grow aligned nanotube arrays with controlled density on crystalline, insulating sapphire substrates, which bear analogy to industry-adopted silicon-on-insulator substrates. On the basis of the nanotube arrays, we demonstrated registration-free fabrication of both top-gated and polymer-electrolyte-gated field-effect transistors with minimized parasitic capacitance. In addition, we have developed a way to transfer these aligned nanotube arrays to flexible substrates successfully. Our approach has great potential for high-density, large-scale integrated systems based on carbon nanotubes for both micro- and flexible electronics.

A Versatile Active Circuit for Realising Floating Inductance, Capacitance, FDNR and Admittance Converter

Abstract: An active circuit suitable for realizing floating inductance, capacitance, FDNR and admittance converter depending on the selection of passive elements of the circuit is presented. The proposed circuit employs only two dual output second-generation current conveyors (DO-CCIIs) and does not require passive element matching. The proposed network has a grounded capacitor for the floating inductance and capacitance simulation. Frequency performance of the circuit is tested using SPICE.

High-precision, fast current source for large-area current-programmed a-Si flat panels

Abstract: Although current-programmed pixel circuits lead to a highly stable amorphous silicon (a-Si) active matrix backplane, they are prone to a long settling time due to the large parasitic capacitance coupled with the low mobility of a-Si thin film transistors (TFTs). This paper presents a fast-current source that can significantly improve the settling time of the a-Si active matrix. Also, to reduce the effect of mismatches a differential offset cancellation technique is introduced.

Design of Inductor Winding Capacitance Cancellation for EMI Suppression

Abstract: In this paper, the parasitics in both DM and CM inductors are first discussed. The methods for both DM and CM inductor winding capacitance cancellation are then proposed. Prototypes are designed and tested, using network analyzer. Finally, the prototypes are applied to practical power converters and EMI is measured. Both small signal measurement and practical EMI measurement prove that the proposed methods can efficiently reduce the effects of winding capacitance and therefore improve the inductor's filtering performance.

Converter circuit design, semiconductor device selection and analysis of parasitics for micropower electrostatic Generators

Abstract: For various medical monitoring and sensing applications it is desirable to power the electronics by scavenging energy from any locally available source. An electrostatic motion-driven generator for low-frequency (human body) motion has been developed by the authors using microelectromechanical system technology. The prototype generates pulses of 250V on a 10-pF capacitor. This paper examines the design of a circuit and semiconductor devices to convert this energy to a low voltage. Because of the very small charge involved, the effects of leakage and parasitic stored charge are important. Converters for this application using silicon-on-insulator metal-oxide-semiconductor field-effect transistors and insulated gate bipolar transistors are compared using physics-based finite-element simulation. The overall effectiveness of the generation process is shown to be composed of several terms which are functions of system parameters such as generator flight time, semiconductor device area, and circuit inductance. It is shown that device area is a compromise between leakage current, charge storage, and on-state voltage. It can, for a given generator and inductance, be optimized to provide the maximum energy yield. Parasitic series inductance is shown to be of little importance to the circuit efficiency; however, parasitic capacitance has a significant influence.

Shielded through-via

Abstract: A shielded through-via that reduces the effect of parasitic capacitance between the through-via and surrounding wafer while providing high isolation from neighboring signals. A shield electrode is formed in the insulating region and spaced apart from the through-via. A coupling element couples at least the time-varying portion of the signal carried on the through-via to the shield electrode. This reduces the effect of any parasitic capacitance between the through-via and the shield electrode, hence the surrounding wafer.

Modeling and analysis of circuit performance of ballistic CNFET

Abstract: With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is seen to be effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.

Inductor winding capacitance cancellation using mutual capacitance concept for noise reduction application

Abstract: In this paper, the properties of mutual capacitance between two capacitors are first discussed. It is found that the effects of mutual capacitance can be represented by two positive or negative capacitors across the two capacitors. These two equivalent capacitors can be used to cancel the parasitic capacitance of inductors. Because the mutual capacitance can be emulated using two small capacitors, the proposed method can easily be implemented in practical components. The prototypes are then built and the cancellation is verified using a network analyzer. Further EMI measurements in a practical power circuit prove that there is a significant improvement in the inductor's filtering performance.

Underlap DGMOS for digital-subthreshold operation

Abstract: Digital circuits operated in the subthreshold region (supply voltage less than the transistor threshold voltage) is suitable for applications requiring ultralow-power and medium frequency of operation. It is also shown that by optimizing the device structure for subthreshold operation, power dissipation can further be reduced. The impact of gate underlap on the effective gate capacitance of double-gate MOS (DGMOS) transistor for digital-subthreshold operation is analyzed in this paper. It shows that with optimum gate underlap, the parasitic fringe capacitances of DGMOS can be significantly reduced resulting in higher performance and lower power consumption. Results on a ring oscillator show that with optimum underlap, 40% improvement in delay can be achieved with 7.3 /spl times/ reduction in power delay product and a 1-bit full-adder circuit can be operated at 1.25 GHz (V/sub dd/=0.2 V) with 6.2 /spl times/ less power than the one with standard (overlap) DGMOS device.

Carbon Nanotube Field-Effect Transistors for High-Performance Digital Circuits—Transient Analysis, Parasitics, and Scalability

Abstract: Silicon-based CMOS is the dominant technology choice for high-performance digital circuits. While silicon technology continues to scale, researchers are investigating other novel materials, structures, and devices to introduce into future technology generations, if necessary, to extend Moore's law. Carbon nanotubes (CNTs) have been explored as a possibility due to their excellent carrier mobility. The authors studied and compared different carbon-nanotube-based field-effect transistors (CNFETs) including Schottky-barrier (SB) CNFETs, MOS CNFETs, and state-of-the-art Si MOSFETs systematically from a circuit/system design perspective. Parasitics play a major role in the performance of CNT-based circuits. The data in this paper show that CNFET design's performance is limited by the gate overlap capacitance and the quality of nanocontacts to these promising transistors. Transient analysis of high-performing single-tube SB CNFET transistors and circuits revealed that 1-1.5 nm is the optimum CNT diameter resulting in best power-performance tradeoff for high-speed digital applications. The authors determined optimal spacing and layout of CNT arrays, an architecture that is most likely required for driving capacitive loads and interconnects in digital applications. CNTs have an intrinsic capability to improve performance, but many serious technological and experimental challenges remain that require more research to harvest their potential

First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier

Abstract: First demonstration of AC gain from a single-walled carbon nanotube transistor is presented. A top-gated carbon nanotube field-effect transistor (CNFET) is configured as a common-source amplifier and frequency response function of the amplifier is measured. Evidence of unambiguous signal amplification is observed in time domain as well as frequency domain up to a unity gain frequency of approximately 560 kHz. The observed roll-off in frequency is solely due to the RC time constant of the measurement apparatus. A specifically designed circuit compatible SPICE model for the CNFET is used to model both DC and AC characteristic with the same set of physical parameters for the first time. Good agreement between measurement and simulation is obtained. For a device without the parasitic load capacitance, the predicted intrinsic unity voltage gain frequency is 29 GHz and the cut-off frequency is ~ 50 GHz.

A Driving Scheme for Active-Matrix Organic Light-Emitting Diode Displays Based on Current Feedback

Abstract: This paper presents a method of driving active-matrix organic light-emitting diode (AMOLED) displays with amorphous silicon (a-Si) thin-film transistors (TFTs). By using current feedback, the method effectively compensates for the effect of shift in the threshold voltage (V T) of a-Si TFTs on the OLED current. A CMOS transresistance amplifier is used as the column driver to cancel the effect of large parasitic capacitance of data lines. An accelerating pulse is used at the start of the programming cycle to improve the settling at low currents. A detailed analysis has been done to investigate the effect of circuit components on the sensitivity of the OLED current to V T shift and the settling behavior of the circuit. Prototypes of pixel circuits and the transresistance amplifier were fabricated in an a-Si TFT process and a 0.8- mum 20-V CMOS technology, respectively. Measurements show less than 5% change in the OLED current for 2.5-V shift in V T of TFTs. Settling times smaller than 50 mus were achieved for parasitic capacitances of 50-200 pF and programming currents as small as 200 nA.

Zero voltage switching buck converter

Abstract: The present invention is directed generally to a buck converter that achieves zero voltage switching (ZVS). According to various embodiments, the buck converter comprises a ZVS circuit for storing reverse recovery current from the diode of the buck converter and using the energy from the reverse recovery current to discharge parasitic capacitance of the primary switch of the buck converter prior to turn-on of the primary switch such that the primary switch turns on with substantially zero voltage across the switch. The ZVS circuit may comprise a capacitor, an auxiliary switch connected in series with the capacitor, and an auxiliary inductor connected in parallel with the series-connected capacitor and auxiliary switch. The control circuit controls the primary switch and the auxiliary switch of the ZVS circuit such that (i) the auxiliary switch and the primary switch are not both on at the same time, and (ii) there is a time interval between the end of the on-time of the auxiliary switch and the beginning of the on-time of the primary switch. The time interval (which may be a fixed duration) is of sufficient duration such that the energy from the reverse recovery current substantially discharges the parasitic capacitance of the primary switch during the time interval. Interleaved embodiments of the buck converter are also disclosed.

Charge-based capacitance measurement for bias-dependent capacitance

Abstract: In this letter, charge-based capacitance measurement (CBCM) is applied to characterize bias-dependent capacitances in a CMOS transistor. Due to its special advantage of being free from the errors induced by charge injection, the operation of charge-injection-induced-error-free CBCM allows for the extraction of full-range gate capacitance from the accumulation region to the inversion region and the overlap capacitance of MOSFET devices with submicrometer dimensions.

Three-phase low noise charge pump and method

Abstract: A low noise charge pump circuit includes a first terminal (8) of a first flying capacitor (Cl) selectively coupled to a first voltage (VCC) during a first recharging phase and a second terminal (7) of the first flying capacitor selectively coupled to a second voltage (GND) during the first recharging phase. The second terminal of the first flying capacitor is coupled to a precharge control circuit (25, 27) during a first parasitic capacitance precharging phase that occurs after the first recharging phase to cause the voltage of the first terminal of the first flying capacitor to equal an output voltage (Vout). The first terminal of the first flying capacitor is coupled to an output conductor (10) conducting the output voltage during a first discharging phase that occurs after the first parasitic capacitance precharging phase. The second terminal of the first flying capacitor is coupled to a discharge control circuit (2, 4) which increases the voltage of the second terminal of the first flying capacitor during the first discharging phase until the output voltage is equal to a regulated value.

Crosstalk canceling pattern for high-speed communications and modular jack having the same

Abstract: Disclosed herein are a crosstalk canceling pattern for high-speed communications and a modular jack having the same, which includes a compensating capacitor on a transmission line to cancel crosstalk due to parasitic capacitance generated between neighboring insert pins, and includes a second compensating capacitor to correct phase mismatch due to parasitic inductance generated in insert pins and transmission lines, when a high-frequency signal is applied The modular jack having the crosstalk canceling pattern for high-speed communications includes a housing, a printed circuit board, a lower contact block, and an upper contact block The hosing includes a plug insert hole, an insert pin locking plate, and a coupling guide part The printed circuit board is a multi-layered structure having a plurality of compensating capacitors The lower contact block is mounted to the lower surface of the printed circuit board The upper contact block is mounted to the upper portion of the lower contact block, and divides UTP cable wires to be connected to IDC terminals

Tuning an RFID reader with electronic switches

Abstract: A reader for an RFID system includes a signal driver for generating an excitation signal and a resonant circuit having an adjustable resonant circuit capacitance for retuning the resonant circuit in response to detuning. The resonant circuit has a capacitance tuning circuit which includes a fine-tuning capacitor having a fine-tuning capacitance and a fine-tuning capacitor switch having an open position and a closed position. The fine-tuning capacitance is added to the adjustable resonant circuit capacitance when the fine-tuning capacitor switch is in the closed position and is removed from the adjustable resonant circuit capacitance when the fine-tuning capacitor switch is in the open position.

Sub-nanosecond monitoring of micro-hole electrical discharge machining pulses and modeling of discharge ringing

Abstract: Monitoring the gap voltage and current in micro-hole electrical discharge machining (EDM) using high-speed data acquisition with 0.5 ns sampling period is conducted. The spark and arc pulses at three stages, namely electrode dressing, drilling, and penetration, of the micro-hole EDM are recorded. The EDM process parameters are setup to use negative polarity to blunt the electrode tip and positive polarity for micro-hole drilling and penetration. A new phenomenon of pre-discharging current is discovered. In the first 20–30 ns of spark and arc pulses, the current starts to rise while the voltage remains the same. Effects of EDM process parameters, including the open voltage, electrode diameter, and polarity, on the rate of spark and arc pulses and electrode feed rate are investigated. A model based on the RLC circuit is developed to study the ringing effect at the end of a discharge. The intrinsic parasitic capacitance and resistance of a RLC circuit are calculated from the decaying voltage signal and compared under two sets of experiments with varying wire electrode diameter and gap voltage to validate the ringing model. The calculation and experimental results validate the proposed RLC model for ringing phenomenon. The model shows the electrode diameter has negligible effect on ringing and high open voltage increases the parasitic resistance and damping in ringing. The monitoring technique and ringing model developed in this research can assist in the selection and optimization of micro-hole EDM process parameters.

Electrical detection of oscillations in microcantilevers and nanocantilevers

Abstract: Precise determination of the resonant frequency, phase, and quality factor in micromechanical and nanomechanical oscillators would permit, among other things, (i) the detection of trace amounts of adsorbed molecules through a shift in the resonant frequency, and (ii) pressure variations in the environment which affect the mechanical damping of the oscillator. The major difficulty in making these measurements in many cases is the ancillary equipment such as lasers or high magnetic fields that must be used. Being able to make precise measurements with a fully electrical actuation and detection method would greatly extend the usefulness of these oscillators. Detecting the oscillation through changes in the capacitance between the oscillator and a counter electrode is difficult because the static capacitance between them as well as the parasitic capacitance of the rest of the circuitry overwhelm the detection. We have found that the charge on a microcantilever or nanocantilever when driven by a nearby counter electrode contains higher harmonics of the driving signal with appreciable amplitude. This allows detection at frequencies well removed from the driving frequency, which increases the signal to background ratio by approximately three orders of magnitude. With this method, we show clear electrical detection of mechanical oscillations in ambient conditions for two systems: Si-based microcantilevers and multiwalled carbon nanotube based nanocantilevers.

Voltage controlled oscillator and wireless transceiver using the same

Abstract: The capacitance of the capacitor with the constant capacitance is equivalently reduced in the capacitance of a resonant capacitor in a voltage control oscillator to increase the variable amount of the capacitance of the resonant capacitor, and to expand an oscillation frequency range. There are provided a differential negative conductance generator circuit having two resonation nodes for differential output, a differential resonant circuit having a variable capacitance that is controlled by voltage control and an inductance connected in parallel to each other, and a differential negative impedance circuit. A resonant circuit and a negative impedance circuit are connected between the resonation nodes. The capacitor with the constant capacitance that occurs between the resonation nodes is reduced by the negative impedance of the negative impedance circuit. The capacitor with the constant capacitance is represented by floating capacitors that occur between one of the resonation nodes and a ground potential and between the other resonation node and the ground potential, respectively.