Showing papers on "Parasitic capacitance published in 2014"

Dead-Time Compensation of Inverters Considering Snubber and Parasitic Capacitance

Abstract: In power electronics drive systems, dead time is used to prevent shoot-through over power devices. However, dead time can lead to distortion of ac output voltages and currents. Various compensation methods have been proposed to overcome this drawback. However, most strategies assume the power switches as ideal switches and the transition from ON to OFF or vice versa is infinitely fast. In this paper, effects of inverter snubber and parasitic capacitance to the switching instants are investigated when doing dead-time compensation. A new dead-time compensation method is presented with the capacitance being considered. It is verified that the compensation becomes more accurate and effective for the specific application after the modification. It is also shown that the proposed compensation can make the inverter system stable and robust. This proposed approach is validated by the experimental results.

Analysis on the influence of the secondary parasitic capacitance to ZVS transient in LLC resonant converter

Abstract: This paper analyzes the (zero voltage switching) ZVS process mechanism considering the parasitic capacitance of the secondary rectifier in an LLC resonant converter and presents the design considerations to guarantee the fully realization of the soft switching. When an LLC resonant converter is used as an unregulated converter (DCX) in telecom applications, the secondary parasitic capacitance has a significant influence on the ZVS process, and the dead time calculation is different from the conventional method. This influence, which is rarely analyzed in the literatures, is presented in this paper. Experimental results of an LLC converter prototype are provided to verify the theoretical analysis.

88- A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors

Abstract: The paper describes an innovative technique to implement a low-power high-speed CMOS interface circuit for differential capacitive sensors. The proposed approach comprises a capacitance to current converter providing current-summing and current-differencing capability. It also exploits an autotuning feedback loop to control the common-mode current, thereby ensuring virtually the same maximum sensitivity and measure accuracy irrespectively of the input parasitic capacitance. Therefore, the main limitation of all previous current-mode techniques is nearly eliminated. Besides, as an additional distinctive aspect, the proposed solution is suitable for both linear- and hyperbolic-type capacitive sensors. To validate the idea an interface circuit was designed in a 65-nm CMOS technology powered from a 2.5-V supply and dissipating 88- μA standby current. Measurements show that relative capacitive sensor variations up to ± 900 fF ( ± 100% of the nominal value) even in presence of a large parasitic capacitance of 2.5 pF are detected in less than 1 μs with a sensitivity of about 5 nA/fF and with an relative error lower than ± 1.5%, without requiring digital calibration.

Modeling of the High-Frequency Rectifier With 10-kV SiC JBS Diodes in High-Voltage Series Resonant Type DC–DC Converters

Abstract: The superior material properties of the wide bandgap silicon carbide (SiC) semiconductors enable excellent device characteristics such as low on-resistance, high breakdown voltage, fast switching speed, high temperature operation, etc. 10-kV SiC junction barrier Schottky (JBS) diode prototype made by Cree was characterized in this paper first. The high-voltage (HV) and high-frequency rectifier consisting of SiC JBS diodes in dc-dc converters can potentially benefit from the device characteristics. However, capacitive current in both forward and reverse recovery process is observed due to the junction capacitance when the SiC JBS diode is turned on and off, which increases the reactive power and reduces the rectifier output power and voltage. To better utilize the devices, the rectifier operation is analyzed in consideration of the impact of the JBS diode parasitic capacitance. Two equivalent circuit models, the series and the parallel input impedance model, are proposed. The distributed junction capacitance of JBS diodes is lumped into the equivalent input capacitance such that the input impedance and output voltage, two critical parameters in HV dc-dc converter design, can be predicted from the models. Experiment setup of SiC JBS diode rectifier was built and the test results verified the modeling work.

An Optimum Design for Integrated Switched-Capacitor Dickson Charge Pump Multipliers With Area Power Balance

Abstract: This letter expands upon an optimum design of integrated switched-capacitor Dickson charge pump multipliers for minimizing the power, which considers the parasitic capacitance of both the top and bottom plates of pump capacitors. This letter also discusses an optimum design with area power balance, and suggests that the number of stages should be e NMIN, where e is 1.5-1.7 and NMIN is the minimum number of stages required to meet the condition that the output current is zero at a given output voltage.

Single-contact transmission for the quasi-wireless delivery of power over large surfaces

Abstract: A method of power transmission is proposed that delivers power through the resonance of a helical receiver with its surrounding stray capacitance. The system operates in a quasi-wireless state where power is transferred over a single connection to a surface much larger than the dimensions of the receiver. This ensures high-efficiency energy transfer over large areas without the need of strong coupling electromagnetic fields. Standard power connectors such as tracks, plugs, and cords may be easily replaced with conductive surfaces or objects such as foil sheets, desks, and cabinets. Presently, the method is experimentally demonstrated at the small scale using loads of up to 50 W at an efficiency of 83% with both bare and insulated surfaces. Simple circuit modeling of the system is presented which shows close agreement with experimental results.

Split-gate organic field-effect transistors for high-speed operation.

Abstract: Split-gate organic field-effect transistors have been developed for high-speed operation. Owing to the combination of reduced contact resistance and minimized parasitic capacitance, the devices have fast switching characteristics. The cutoff frequencies for the vacuum-evaporated devices and the solution-processed devices are 20 and 10 MHz, respectively. A speed of 10 MHz is the fastest device reported so far among solution-processed organic transistors.

Influence of Multijunction Ga/As Solar Array Parasitic Capacitance in S3R and Solving Methods for High-Power Applications

Abstract: This paper deals with the influence produced by the solar array parasitic capacitance and its solving methods in the sequential switching shunt regulator (S3R). Nowadays, the usage of triple-junction Ga/As solar cells with larger parasitic capacitance has prompted new problems about power losses, steady state, and dynamic response in the S3R, especially for high section current, voltage applications. Effects of parasitic capacitance on voltage ripple, “double sectioning,” phase margin, and output impedance are represented and analyzed, and turn-off delay caused by parasitic capacitance is mathematically modeled. A novel shunt regulator topology passive and active shunt regulator (PASR) with low switching losses, low mass, and short turn-off time delay is proposed. To further reduce the impact of delay, nonlinear control is added in the control loop, achieving better performances in the stability margin, output impedance, and dynamic performance. Simulation and experimental results are provided to validate the proposed PASR together with nonlinear control scheme.

Switchless charge-discharge circuit for electrical capacitance tomography

Abstract: The main factor limiting the performance of electrical capacitance tomography (ECT) is an extremely low value of inter-electrode capacitances. The charge-discharge circuit is a well suited circuit for a small capacitance measurement due to its immunity to noise and stray capacitance, although it has a problem associated with a charge injected by the analogue switches, which results in a dc offset. This paper presents a new diode-based circuit for capacitance measurement in which a charge transfer method is realized without switches. The circuit was built and tested in one channel configuration with 16 multiplexed electrodes. The performance of the elaborated circuit and a comparison with a classic charge-discharge circuit are presented. The elaborated circuit can be used for sensors with inter-electrode capacitances not lower than 10 fF. The presented approach allows us to obtain a similar performance to the classic charge-discharge circuit, but has a simplified design. A lack of the need to synchronize the analogue switches in the transmitter and the receiver part of this circuit could be a desirable feature in the design of measurement systems integrated with electrodes.

Variable capacitance element and high-frequency device

Abstract: A high-frequency device includes an antenna coil, a variable capacitance element, and an RFIC. The variable capacitance element is configured by capacitor units in each of which a ferroelectric film is sandwiched between capacitor electrodes, and a capacitance value changes according to a control voltage applied between the capacitor electrodes. A control voltage application circuit configured by a plurality of resistance elements of different resistance values, and a resistance element of the variable capacitance element unit configured to apply a control voltage to the variable capacitance element are arranged in a layered manner above the capacitor unit. Thus, a variable capacitance element and a high-frequency device that includes a control voltage application circuit eliminating problems such as distortion due to active elements and growing IC size along with complication of circuit architecture, and ensuring reliability on impact due to falling or the like, are provided.

Analysis of the Voltage–Time Dilemma of Metal Oxide-Based RRAM and Solution Exploration of High Speed and Low Voltage AC Switching

Abstract: In this paper, the ac electrical characteristics of metal oxide-based resistive random access memory are investigated based on a developed compact model and the experiment. The voltage-time dilemma phenomenon and the impacts of critical factors on resistive switching speed are addressed. Based on predictions of the model, the small parasitic capacitance, low target high resistance, and large thermal resistance are beneficial to accelerate the resistive switching speed both in SET and RESET processes. The high SET speed and low SET voltage can be achieved by tuning the activation energy of oxygen vacancies. While for the RESET process, the barriers of the release of oxygen ions from electrode and the hopping in resistive switching layer should be turned down simultaneously for high switching speed and low operation voltage.

Optimal winding design of a pulse transformer considering parasitic capacitance effect to reach best rise time and overshoot

Abstract: High voltage and high frequency pulses are widely used in industrial applications such as klystron modules, radar application, plasma technology, and so on. Transforming such a pulse with magnitude of thousands volt requires special transformers. Considering its frequency requirements which vary from hundreds to thousands Hertz, effects of parasitic capacitance may change the expected results. In this paper a specific method is proposed to optimize the design of both high voltage (HV) and low voltage (LV) windings, to reach the best rise time and overshoot performance. This method is based on both calculations of equivalent circuit and finite element analysis (FEA). Among the various topologies represented in the literatures, cone winding type pulse transformer is selected in which by changing its windings angle, it can be modified to parallel winding type. Initially analytical study in pulse transformer rise time equivalent circuit is performed to find the best cone angle between the windings and also the best distance between the bottom of windings to reach the optimum output parameters of pulse transformer such as fast rise time and minimum overshoot. In this analysis the lumped parameters of the equivalent circuit are calculated based on the stored energy between the windings. Afterwards sensitivity of the response to the load and source parameters variations is calculated in order to find the best distance and the angle between the windings. In the meantime, the distributed parasitic capacitances are extracted by using FEA to exert as circuit elements, in the electromagnetic model of pulse transformer. Finally a transient analysis is executed on the pulse transformer model containing distributed capacitances. The results of this analysis prove that the winding design using the distributed elements effects shows good results considering pulse shape.

A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC) for CMOS Image Sensors

Abstract: A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

Analysis, Design, and Implementation of the Class-E ZVS Power Amplifier With MOSFET Nonlinear Drain-to-Source Parasitic Capacitance at any Grading Coefficient

Abstract: In this paper, analytical expressions for waveforms and design relationships are derived for the class-E power amplifier with the MOSFET nonlinear drain-to-source parasitic capacitance under the subnominal operation, i.e., only zero-voltage switching (ZVS) condition, for any grading coefficient m of the MOSFET body junction diode and 50% duty ratio. Only the MOSFET nonlinear drain-to-source parasitic capacitance is used for the analysis of the class-E ZVS power amplifier, and its nonlinearity is determined by the grading coefficient m. The switch voltage waveform does not satisfy the class-E ZVS switching condition when only the linear shunt capacitance is considered. The grading coefficient m is used as an adjustment parameter that provides accurate design to satisfy the given output power and peak switch voltage simultaneously. Therefore, the grading coefficient m is the important parameter to satisfy the class-E ZVS condition and given design specifications, which is the most important result in this paper. Additionally, the output power capability and maximum operating frequency are affected by the grading coefficient m. The analytical expressions are obtained by considering the grading coefficient m as an adjustment parameter, which is validated by PSpice simulations and laboratory experiments. The measurement and PSpice simulation results agreed with the analytical expressions quantitatively, which denotes the usefulness and effectiveness of our obtained analytical expressions.

An X-Band Switchless Bidirectional GaN MMIC Amplifier for Phased Array Systems

Abstract: An X-Band switchless bidirectional amplifier (BDA) in a 0.25 μm gallium-nitride (GaN) on SiC process is introduced. The proposed bidirectional amplifier comprises of a 1 W power amplifier (PA) and a low noise amplifier (LNA) for T/R modules of phased array systems without any aid of switches. In receive mode, the BDA has flat gain of 20.2±1 dB and shows wideband input matching at 8 to 12 GHz. The minimum noise figure is 4.3 dB at 10.4 GHz and below 5 dB across the X-Band. In transmit mode, the small signal gain of the PA is 27±3 dB, its P1 dB is about 27 dBm, and its saturated output power is over 30 dBm at 8 to 12 GHz. The PA consumes 220 mA of quiescent current with 20 V power supply. While one mode is working, the other mode transistors are off and their parasitic capacitance has been already considered in design stage to minimize performance degradation and leakage. The total chip size is 2.5 mm×1.87 mm including pads.

In-circuit-measurement of parasitic elements in high gain high bandwidth low noise transimpedance amplifiers.

Abstract: Parasitic elements play an important role in the development of every high performance circuit. In the case of high gain, high bandwidth transimpedance amplifiers, the most important parasitic elements are parasitic capacitances at the input and in the feedback path, which significantly influence the stability, the frequency response, and the noise of the amplifier. As these parasitic capacitances range from a few picofarads down to only a few femtofarads, it is nearly impossible to measure them accurately using traditional LCR meters. Unfortunately, they also cannot be easily determined from the transfer function of the transimpedance amplifier, as it contains several overlapping effects and its measurement is only possible when the circuit is already stable. Therefore, we developed an in-circuit measurement method utilizing minimal modifications to the input stage in order to measure its parasitic capacitances directly and with unconditional stability. Furthermore, using the data acquired with this measurement technique, we both proposed a model for the complicated frequency response of high value thick film resistors as they are used in high gain transimpedance amplifiers and optimized our transimpedance amplifier design.

On Evaluation of Inductance, DC Resistance, and Capacitance of Coaxial Inductors at Low Frequencies

Abstract: A priori evaluations of inductance, stray capacitance, and dc resistance are important aspects in optimizations of inductors. In this paper, analytical formulas of the inductance (self and mutual), dc resistance (solid and litz wires), and the stray capacitances of coaxial inductors were derived for both hexagonal and orthogonal windings. Possible imperfections that occurred during the fabrication process were accounted by the inclusion of axial and azimuth filling factors into the formulations. The formulas presented here were validated using several coaxial coils with rectangular cross sections as reported in the literature and double tested by measurements. Discrepancies between estimated and measured values were less than 1%. The advantage of the present formulation is that optimization efforts are addressed at the earliest stages possible of inductor conception and construction.

Touch display device, drive circuit and drive method

Abstract: The invention provides a touch display device, a drive circuit and a drive method The touch display device comprises a common electrode and the drive circuit; the common electrode is disposed between a first substrate and a second substrate; the common electrode is used as a touch sensing electrode during a touch sensing phase; the drive circuit is used for providing the common electrode with a first signal for touch detection; the drive circuit is further used for providing a gate line with a second signal during the touch sensing phase; the second signal enables a thin-film transistor to be off and decreases charge-discharge capacity of a capacitor formed by the common electrode and the gate line, and/or, the drive circuit is used for providing a third signal during the touch sensing phase, and the third signal decreases charge-discharge capacity of the capacitor formed by a common electrode and a data line The invention further provides the corresponding drive circuit and a drive method The interference of stray capacitance upon touch detection can be reduced, and touch detection precision can be improved

Shielded Capacitor Sensor System For Medical Applications and Method

Abstract: A measurement system for measuring a parameter of the muscular-skeletal system is disclosed. The measurement system comprises a capacitor, a signal generator, a digital counter, counter register, a digital clock, a digital timer, and a data register. The sensor of the measurement system is the capacitor. The measurement system generates a repeating signal having a measurement cycle that corresponds to the capacitance of the capacitor. The capacitor comprises more than one capacitor mechanically in series. Electrically, the capacitor comprises more than one capacitor in parallel. In one embodiment, the capacitor includes a dielectric layer comprising polyimide. A force, pressure, or load is applied to the capacitor that elastically compresses the device. The capacitor is shielded from parasitic coupling and parasitic capacitance.

Bandwidth enhancement technique for CMOS RGC transimpedance amplifier

Abstract: A technique that can increase the bandwidth of a regulated cascode (RGC) transimpedance amplifier (TIA) is presented. The proposed new RGC input topology with a positive amplifier and an inductor enables the control of the input impedance of the circuit and isolates the large input parasitic capacitance. Using this mode the dominant pole of the input node is shifted up to a high frequency, and then the bandwidth of the CMOS RGC TIA is improved. To verify the feasibility of the proposed technique, the CMOS RGC TIA is implemented using a 1P6M 0.18 μm RF CMOS technology. The 3 dB bandwidth of 4.98 GHz is measured in the presence of a 0.5 pF photodiode capacitance with a 1.8 V supply voltage. The measured result shows that the bandwidth of the TIA can increase by about 2 GHz larger than that with the conventional RGC configuration.

High resolution capacitance sensor array for real-time monitoring of cell viability

Abstract: Capacitance based cell sensing has shown promising results for monitoring cell viability. Studies have shown direct correlation between cell health and measured capacitance. Prior sensors have used charge based capacitance measurement, which has limitations in offset correction, range, and resolution. An alternative approach to monitoring small changes in electrode capacitance is to measure frequency change of a current controlled ring oscillator containing a sensing electrode that acts as a variable capacitor. This sensor design has no need for on-chip offset correction, because the range of the digital output of the chip depends on the counter size rather than input voltage. In addition, the resolution for this sensor is limited only by the amount of read time given to each pixel. For an oscillation frequency of 40 MHz the sensors are expected to achieve a resolution of 2.6 aF. The sensor has been incorporated into a 4×4 array prototype which will be packaged for operation in cell culture and used in viability studies of mammalian cells.

Minimization of the transformer inter-winding parasitic capacitance for modular stacking power supply applications

Abstract: In an isolated power supply, the inter-winding parasitic capacitance plays a vital role in the mitigation of common mode noise currents created by fast voltage transient responses. The lower the transformer inter-winding capacitance, the more immune the power supply is to fast voltage transient responses. This requirement is even more critical for modular stacking applications in which multiple power supplies are stacked. This paper addresses the issue by presenting a detailed analysis and design of an unconventional isolated power supply that uses a ring core transformer with a very low inter-winding parasitic capacitance of 10 pF. Considering its output power of 300 W, this approach yields about 0.033 pF/W inter-winding capacitance over output power, approximately thirty times lower than existing approaches in the literature. This makes the converter a suitable solution for modular stacking of fast voltage switching applications. Mathematical derivation of the inter-winding capacitance and experiments are carried out to prove the validity of the approach.

Improving ESD robustness of stacked diodes with embedded SCR for RF applications in 65-nm CMOS

Abstract: To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit must be carefully designed. In this work, stacked diodes with embedded silicon-controlled rectifier (SCR) to improve ESD robustness was proposed for RF applications. Experimental results in 65-nm CMOS process show that the proposed design can achieve low parasitic capacitance, low turn-on resistance, and high ESD robustness.

Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

Abstract: Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency (fT). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

System and Method for a Switchable Capacitance

Abstract: In accordance with an embodiment, a switchable capacitance circuit includes a plurality of capacitance-switch cells that each have a capacitance circuit having a capacitance between a first terminal and a second terminal of the capacitance circuit, and a semiconductor switching circuit including a first terminal coupled to the first terminal of the capacitance circuit, a plurality of series connected radio-frequency (RF) switch cells having a load path and a common node. Each of the plurality of series connected RF switch cells has a switch transistor and a gate resistor having a first end coupled to a gate of the switch transistor and a second end coupled to the common node. The switchable capacitance circuit also includes a resistance circuit having a first end coupled to the common node and a second end coupled to a control node.

Cross-correlation measurement of quantum shot noise using homemade transimpedance amplifiers.

Abstract: We report a cross-correlation measurement system, based on a new approach, which can be used to measure shot noise in a mesoscopic conductor at milliKelvin temperatures In contrast to other measurement systems in which high-speed low-noise voltage amplifiers are commonly used, our system employs homemade transimpedance amplifiers (TAs) The low input impedance of the TAs significantly reduces the crosstalk caused by unavoidable parasitic capacitance between wires The TAs are designed to have a flat gain over a frequency band from 2 kHz to 1 MHz Low-noise performance is attained by installing the TAs at a 4 K stage of a dilution refrigerator Our system thus fulfills the technical requirements for cross-correlation measurements: low noise floor, high frequency band, and negligible crosstalk between two signal lines Using our system, shot noise generated at a quantum point contact embedded in a quantum Hall system is measured The good agreement between the obtained shot-noise data and theoretical predictions demonstrates the accuracy of the measurements

A robust parasitic-insensitive successive approximation capacitance-to-digital converter

Abstract: In this paper, we present a capacitive sensor digital interface circuit using true capacitance-domain successive approximation that is independent of supply voltage. Robust operation is achieved by using a charge amplifier stage and multiple comparison technique. The interface circuit is insensitive to parasitic capacitances, offset voltages, and charge injection, and is not prone to noise coupling. The proposed design achieves very low temperature sensitivity of 25ppm/°C. A coarse-fine programmable capacitance array allows digitizing a wide capacitance range of 16pF with 12.5-bit quantization limited resolution in a compact area of 0.07mm2. The fabricated prototype is experimentally verified using on-chip sensor and off-chip MEMS capacitive pressure sensor.

Effects of Stray Capacitance to Ground in Bipolar Material Impedance Measurements Based on Direct-Contact Electrodes

Abstract: Bipolar material impedance measurements are easier to implement than tetrapolar measurements but are more affected by electrode impedance. This effect can be reduced by measuring at a high-enough frequency albeit with the risk of deviations due to stray capacitances. High frequency measurements intended to reduce the influence of material conductivity when its permittivity is of interest also suffer from the effects of parasitic capacitances. In this paper, the effect of stray capacitance to ground in bipolar material impedance measurements implemented with direct-contact electrodes has been analyzed to identify the relevant parameters that determine the best frequency range to measure the conductivity or permittivity of the material when impedance analyzers based on an auto-balancing bridge are used. Stray capacitance to ground yields inductive effects proportional to it and also resistive and capacitive effects. If the ratio between this stray capacitance and the capacitance of the material under test is high enough, the modulus of the measured impedance can display a peak at relatively low frequency (about 100 kHz) and its phase angle can become positive. The consequences are that the best estimate of the conductivity of the material is that obtained from the modulus of the impedance at about midrange between the characteristic frequency of electrodes and that of the material, whereas the permittivity cannot be estimated from the impedance modulus measured at high frequency unless the sample capacitance is much larger than its capacitance to ground and propagation effects are negligible.