Showing papers on "Parasitic capacitance published in 2017"

LLC Converters With Planar Transformers: Issues and Mitigation

Abstract: The use of $LLC$ resonant converters has gained popularity in multiple applications that require high conversion efficiency and galvanic isolation. In particular, many applications like portable devices, flat TVs, and electric vehicle battery chargers require demanding slim-profile packaging and enforce the use of planar transformers (PTs) with low-height, low leakage inductance, excellent thermal characteristics, and manufacturing simplicity. The main challenge in successfully designing $LLC$ converters with PT resides in controlling high-parasitic capacitances produced by large overlapping layers in PT windings. When the parasitic capacitances are not controlled, they severely impair the converters’ performance and regulation, and limit the application of PTs in high-frequency $LLC$ converters. This paper characterizes the PT capacitance issue in detail and proposes mitigation strategies to improve the performance of $LLC$ converters with PTs. A systematic analysis is performed, and six PT winding layouts are introduced and benchmarked with a traditional design. As a result of the investigation, an optimized structure is obtained, which minimizes both the interwinding capacitance and ac resistance, while improving the regulation performance of $LLC$ converters. Experimental measurements are presented and show a significant reduction of parasitic capacitance by up to 21.2 intra- and 16.6 interwinding capacitances, without compromising resistance. This substantial capacitance reduction has a tangible effect on the regulation performance of $LLC$ resonant converters. Experimental results of the proposed PT structure in a 1.2 kW $LLC$ resonant converter show a reduction in common-mode noise, extended output voltage regulation, and improved overall efficiency of the converter.

A Multilevel Transformerless Inverter Employing Ground Connection Between PV Negative Terminal and Grid Neutral Point

Abstract: For the safe operation of transformerless grid connected photovoltaic (PV) inverters, the issue of common mode (CM) leakage current needs to be addressed carefully. In this paper, a novel multilevel transformerless inverter topology is proposed, which completely eliminates CM leakage current by connecting grid neutral point directly to the PV negative terminal, thereby bypassing the PV stray capacitance. It provides a low-cost solution consisting of only four power switches, two capacitors, and a single filter inductor. As compared to half-bridge topologies, with this inverter a minimum of 27% and maximum of 100% more output voltage is obtained for the same dc-link voltage. The proposed inverter is analyzed in detail and its switching pattern to generate multilevel output while maintaining the capacitor voltage is discussed. Simulations and experiments results confirm the feasibility and good performance of the proposed inverter.

NbOx based oscillation neuron for neuromorphic computing

Abstract: In a neuromorphic computing system, the complex CMOS neuron circuits have been the bottleneck for efficient implementation of weighted sum operation. The phenomenon of metal-insulator-transition (MIT) in strongly correlated oxides, such as NbO2, has shown the oscillation behavior in recent experiments. In this work, we propose using a MIT device to function as a compact oscillation neuron, achieving the same functionality as the CMOS neuron but occupying a much smaller area. Pt/NbOx/Pt devices are fabricated, exhibiting the threshold switching I-V hysteresis. When the NbOx device is connected with an external resistor (i.e., the synapse), the neuron membrane voltage starts a self-oscillation. We experimentally demonstrate that the oscillation frequency is proportional to the conductance of the synapse, showing its feasibility for integrating the weighted sum current. The switching speed measurement indicates that the oscillation frequency could achieve >33 MHz if parasitic capacitance can be eliminated.

Parasitic Inductance and Capacitance-Assisted Active Gate Driving Technique to Minimize Switching Loss of SiC MOSFET

Abstract: High di/dt and dv/dt of SiC MOSFET cause a considerable amount of overshoot in device voltage and current during switching transients in the presence of inverter layout parasitic inductance and load parasitic capacitance. The excessive overshoots in device voltage and current cause failure of the device. Moreover, these uncontrolled overshoots increase the switching loss in the inverter. It is difficult to reduce parasitic inductance beyond a certain point. This paper proposes an active gate driving technique, which allows inverter to operate with moderate amount of layout parasitic inductance and load parasitic capacitance. The proposed technique dramatically reduces switching loss of the SiC MOSFET with the help of existing parasitic elements. The proposed switching loss reduction technique is termed as quasi zero switching . The developed active gate driver has been tested in a double pulse test setup and a 10 kW two-level voltage source inverter driving an induction motor.

Two-Capacitor Transformer Winding Capacitance Models for Common-Mode EMI Noise Analysis in Isolated DC–DC Converters

Abstract: For isolated dc–dc power converters, the interwinding parasitic capacitance of the transformer is usually one of the main paths for common-mode (CM) noise. In order to simplify the CM noise analysis, this paper proposes a two-capacitor transformer winding capacitance model. The model is derived based on general conditions so it can be applied to different isolated converter topologies. A measurement technique is also proposed to obtain the lumped capacitance for the model. The CM noise models of several isolated converter topologies are analyzed with the proposed two-capacitor transformer winding capacitance model to achieve simplicity. Finally, the proposed transformer winding capacitance model and measurement technique are verified by simulations and experiments.

Integrating Two Stages as a Common-Mode Transformerless Photovoltaic Converter

Abstract: A single-phase common-mode transformerless grid-connected photovoltaic (PV) converter, which is based on the integration of two stages, is proposed in this paper. Transformer elimination in grid-connected PV systems has many advantages. It not only reduces cost, size, and weight but also increases the complete system efficiency. Since there is no galvanic isolation between grid and PV array, a leakage current may appear due to the PV parasitic capacitance to the ground, if this is not taken into account in the converter design. This paper presents a dc/dc boost converter integrated with a full-bridge inverter. The integration of these two stages reduces the ground leakage current. The neutral line of the grid is directly connected to the negative terminal of the PV array, eliminating any possibility of leakage current in this terminal. The principle of operation of the transformerless converter is analyzed, and a 200-W topology is experimentally tested.

Impact of Parasitic Capacitance and Ferroelectric Parameters on Negative Capacitance FinFET Characteristics

Abstract: In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently. An experimental NC-FinFET device is accurately modeled and the experimentally calibrated parameters are used to analyze the NC-FinFETs device performance and its dependence on several key parameters.

Leakage Current Mitigation in Photovoltaic String Inverter Using Predictive Control With Fixed Average Switching Frequency

Abstract: This paper proposes and validates model predictive control as an alternative control strategy for H-bridgeneutral-point-clamped (H-NPC) converters for single-phase grid-tied string photovoltaic (PV) systems. The presented control scheme achieves good quality current waveforms with unity power factor, dc-link voltage control, and neutral-point voltage minimization. Furthermore, the predictive controller has been further enhanced by including an average device switching frequency restriction and a $dv/dt$ mitigation. The main contribution of this paper is the avoidance of the potential leakage current due to parasitic capacitance of the PV modules by using a predictive model based control technique instead of modulated schemes and eliminating high-frequency common-mode voltage components. Experimental results during steady state and dynamic operation are presented to illustrate the behavior of the H-NPC converter commanded by the proposed control scheme.

Passivity Enhancement of Grid-Tied Converters by Series LC-Filtered Active Damper

Abstract: The series LC -filtered active damper can be used for stabilizing a grid converter tied to the nonideal grid. Its operation principle is to mimic a damping resistance at the resonance frequencies appearing in the grid. However, the selection of the damping resistance has not been fully analyzed in the literature. Its effect with parasitic capacitance present in the grid has also usually been ignored, even though it may bring new challenges to the active damper. To address these issues, passivity is applied to study the grid converter stability before the understanding gained is used for formulating a damping resistance selection method. The method formulated can further be improved by admittance shaping so that system stability can always be ensured even when considering grid parasitic capacitance and control imperfection. Experimental results obtained have verified the expectations, and, hence, the suitability of the presented methods for the series LC -filtered active damper.

Edge-Pursuit Comparator: An Energy-Scalable Oscillator Collapse-Based Comparator With Application in a 74.1 dB SNDR and 20 kS/s 15 b SAR ADC

Abstract: This paper presents a new energy-efficient ring oscillator collapse-based comparator, named edge-pursuit comparator (EPC). This comparator automatically adjusts the performance by changing the comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. Furthermore, a detailed analysis of the EPC in the phase domain shows improved energy efficiency over conventional comparators even without energy scaling, and wider resolution tuning capability with small load capacitance and area. The EPC is used in a successive-approximation-register analog-to-digital converter (SAR ADC) design, which supplements a 10 b differential coarse capacitive digital-to-analog converter (CDAC) with a 5 b common-mode CDAC. This offers an additional 5 b of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40 nm CMOS shows 74.12 dB signal-to-noise and distortion ratio and 173.4 dB Schreier Figure-of-Merit. With the full ADC consuming 1.17 $\mu \text{W}$ , the comparator consumes 104 nW, which is only 8.9% of the full ADC power, proving the comparator’s energy efficiency.

Simulation and structure optimization of triboelectric nanogenerators considering the effects of parasitic capacitance

Abstract: Parasitic capacitance is an unavoidable and usually unwanted capacitance that exists in electric circuits, and it is the most important second-order non-ideal effect that must be considered while designing a triboelectric nanogenerator (TENG) because its magnitude is comparable to the magnitude of the TENG capacitance. This paper investigates the structure and performance optimization of TENGs through modeling and simulation, taking the parasitic capacitance into account. Parasitic capacitance is generally found to cause severe performance degradation in TENGs, and its effects on the optimum matching resistance, maximum output power, and structural figures-of-merit (FOMs) of TENGs are thoroughly investigated and discussed. Optimum values of important structural parameters such as the gap and electrode length are determined for the different working modes of TENGs, systematically demonstrating how these optimum structural parameters change as functions of the parasitic capacitance. Additionally, it is demonstrated that the parasitic capacitance can improve the height tolerance of the metal freestanding-mode TENGs. This work provides a theoretical foundation for the structure and performance optimization of TENGs for practical applications and promotes the development of mechanical energy-harvesting techniques.

Applying Variable-Switching-Frequency Variable-Phase-Shift Control and E-Mode GaN HEMTs to an Indirect Matrix Converter-Based EV Battery Charger

Abstract: An indirect matrix converter is employed directly converting the grid ac to the battery voltage, with the dual-active-bridge taking care of the power factor correction and power delivery simultaneously. Such circuit is regarded as one candidate of the high-efficiency and high-power-density electric vehicle on-board chargers, if the double-frequency current ripple to the battery is tolerated. Instead of optimizing the overall charger, this paper is focused on adopting variable switching frequency with multiple phase shifts to accommodate the wide input range (80–260 $V_{\mathrm{ ac}}$ ) and output range (200 V–450 $V_{\mathrm{ dc}}$ ). In addition to the phase shift between the transformer primary-side and secondary-side voltage, one extra phase shift is added to the primary-side H-bridge when the instantaneous input voltage is higher than the reflected output, otherwise, to the secondary side. The goal is to secure zero-voltage-switching for all switches at all voltage range. Such control strategy is further optimized incorporating with the switch parasitic capacitance and dead-band settings. To further enhance the charger performance, GaN HEMTs are equipped to the on-board charger aiming at higher efficiency and higher power density than Si devices. Experimental results indicated that such charger with proposed control strategy embraces the peak efficiency of >97% at 7.2 kW and a power density of ~4 kW/L.

Switched Substrate-Shield-Based Low-Loss CMOS Inductors for Wide Tuning Range VCOs

Abstract: A switched substrate-shield inductor (SSI) topology in bulk CMOS is proposed which minimizes parasitic capacitance and substrate losses, while tuned magnetically induced currents facilitate inductor tunability. The high frequency behavior of the induced current is analyzed, resulting in intuitive insights and design guidelines for a high-performance SSI. An SSI prototype in 65-nm bulk CMOS achieves 34% inductance tunability with a quality factor of >10.3. A voltage-controlled oscillator (VCO) using SSI achieves 40.3% tuning range, from 21 to 31.6 GHz, and a phase noise of −119.1 ± 3.7 dBc/Hz at 10-MHz offset frequencies. The VCO core consumes 4.3 ± 0.2 mW from a 1-V supply.

Characterization and Analysis of an Innovative Gate Driver and Power Supplies Architecture for HF Power Devices With High dv/dt

Abstract: This paper presents a specific architecture for a low-side/high-side gate driver implementation for power devices running at high switching frequencies and under very high switching speeds. An electromagnetic interference (EMI) optimization is done by modifying the parasitic capacitance of the propagation paths between the power and the control sides, thanks to a specific design of the circuit. Moreover, to reduce the parasitic inductances and to minimize the antenna phenomenon, the paper studies which elements of the drivers’ circuitry must be brought as close as possible to the power parts. This is important when the ambient temperature of the power device becomes critical, for instance, in automotive and aeronautic applications. Simulations and experiments validate the advantages of the proposed architecture on the conducted EMI problem.

Self-Capacitance of Single-Layer Inductors With Separation Between Conductor Turns

Abstract: This letter presents the technique for estimating the self-capacitance of single-layer air-core solenoid inductors with separation between the insulated turns. In single-layer air-core inductors, the self-capacitance is due to the conductor turn-to-turn capacitances. The analytical framework to determine the turn-to-turn capacitances of single-layer air-core inductors with uniformly and nonuniformly separated conductor turns is established. The influence of the wire insulation coating is taken into consideration. A representative design example of a single-layer air-core inductor is presented and its self-capacitance and self-resonant frequency are predicted. The presented analytical approach was tested by experimental measurements on the designed inductor. The derived analytical expressions are useful for designing air-core inductors for high frequency (HF) and very HF applications such as electromagnetic interference/electromagnetic compatibility filters and radio and TV transmitters.

Experimental Extraction of Parasitic Capacitances for High-Frequency Transformers

Abstract: Parasitic capacitances of the high-frequency (HF) transformer used in dc–dc converter impact harmonic analysis of the transformer and interactions with the converter. Resonant frequencies of open- and short-circuit impedances characteristics (ICs) have been widely used to extract parasitic capacitances of HF transformers, but it was reported that some resonant frequencies were unobtainable as they were too high where the ICs fluctuated heavily, and parasitic capacitances remained unevaluated. In this paper, resonance features of ICs and voltage transfer characteristics (TCs) are investigated, and a new frequency of voltage TC is used for extracting parasitic capacitances. By analyzing inner links of known impedance resonant frequencies, why and which resonant frequencies are likely to be unobtainable is revealed. Furthermore, a new frequency corresponding to zero of TC, accounting for parallel resonance between leakage inductance and mutual capacitance of the two windings, is used to extract parasitic capacitances. With this new frequency mutual capacitance of the windings is evaluated, and missing equation due to unobtainable impedance resonant frequency is added. Besides, merits and limitations of extracting parasitic capacitances based on ICs and TCs are analyzed. These techniques are verified with several HF transformer prototypes in the laboratory.

Sub-60 mV/dec ferroelectric HZO MoS 2 negative capacitance field-effect transistor with internal metal gate: The role of parasitic capacitance

Abstract: Steep-slope MoS 2 NC-FETs with ferroelectric HZO and internal metal gate in the gate dielectric stack are demonstrated SS less than 50 mV/dec is obtained for both forward and reverse gate voltage sweeps, with minimum SSfor = 376 mV/dec and minimum SS Rev = 422 mV/dec A second minimum of SSr ev as low as 83 mV/dec can be measured as the result of dynamic switching at high speed in ferroelectric HZO The impact of parasitic capacitance on SS and dynamic hysteresis is systematically studied by both experiment and dynamic simulation

Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications

Abstract: This work discusses the capacitance–voltage (C–V) analysis and frequency dependent capacitance of In2O5Sn (Tin Oxide) gate electrode Recessed Channel (TGRC) MOSFET with an aim to examine the effectiveness of In2O5Sn (Transparent) as a gate material on parasitic capacitance which prominently influences the current driving capability and thus, the switching performance. Moreover, capacitance dependent parameters such as Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) are also assessed and found that, TFP increases to 6.33 times in comparison to metal gate RC MOSFET owing to a noticeable reduction in parasitic capacitance (Cgg = Cgs + Cgd), due to which EDP and GBP also improve considerably and thus reflects its effectiveness in RF amplifiers and receivers. In addition, the effect of parameter variation such as gate length (Lg) and negative junction depth (NJD) of TGRC is also observed, and results reveal that with Lg = 20 nm and NJD = 5 nm, TGRC unveils outstanding switching performance which is desirable for low power ULSI applications.

Mitigation Method of the Shaft Voltage According to Parasitic Capacitance of the PMSM

Abstract: This study proposes the shaft voltage mitigation method according to change in parasitic capacitances of a permanent magnet synchronous motor. To consider the shaft voltage reduction in the initial motor design process without any filter, the parasitic capacitances affecting the shaft voltage are calculated using the motor geometry parameters. Then, the shaft voltage is analyzed according to change in parasitic capacitances using the equivalent circuit model and the torque characteristic is also analyzed to effectively mitigate the shaft voltage. As a result, the rotor-to-winding is determined as an appropriate parameter to mitigate the shaft voltage among the parasitic capacitances, because it affects the shaft voltage and does not affect the output torque. Finally, the shaft voltage mitigation method according to variation of rotor-to-winding capacitance is verified by experiment.

Dual LiNbO3 Crystal-Based Batteryless and Contactless Optical Transient Overvoltage Sensor for Overhead Transmission Line and Substation Applications

Abstract: Advanced high-voltage and overvoltage measurement techniques are required for smart grid construction. The existing overvoltage measurement methods that are currently used for power system measurements are mostly based on the use of electromagnetic voltage transformers and capacitive voltage transformers, which have contradiction in measuring accuracy, measuring distance, antijamming, and system compatibility. A batteryless sensor for contactless measurement of the overvoltage on overhead transmission lines based on a combination of the electrooptic effect in LiNbO3 with stray capacitance in the air is designed in this work. On the basis of this design, a dual-crystal structure-based electrooptic conversion unit is presented that eliminates the natural birefringence and improves the operating stability of the sensor. Testing platforms were set up to measure the characteristics of the sensor in thermal stability. In combination with a data acquisition device, the newly designed sensor was applied to online monitoring of the overvoltage in the ac bus and the overhead transmission lines of a 500-kV transformer station and a ±500-kV convertor station in the China Southern Power Grid.

Fine Tuning of an Inductive Link Through a Voltage-Controlled Capacitance

Abstract: Wireless power transfer is a technique usually based on an inductive link, used for delivering energy to remote devices. The power of different applications ranges from microwatts to hundreds of kilowatts, e.g., in biomedical implants and electric vehicles. The transferred power is highly dependent on the relative position between the inductive link coils. Many studies have been presented considering static or quasi-static conditions, based on a fixed tuned circuit. However, when the coils are not stationary, the inductive link must be dynamically tuned to keep the designed output power. This paper presents a methodology for dynamically tune the inductive link by means of a variable capacitance. A voltage-controlled capacitance using concepts of the negative impedance converter and capacitance multiplier is proposed. The phase angle between the input voltage and current is used as the error signal to control the variable capacitance and keep the output power operating point. The experimental evaluation shows that the proposed methodology can significantly improve the power delivered to the load in comparison to a fixed inductive link.

Comparative Analysis of Semiconductor Device Architectures for 5-nm Node and Beyond

Abstract: This letter, for the first time, investigates interactive logic cell schemes and transistor architecture scaling options for 5-nm technology node (N5) and beyond. The proposed novel transistors, such as Hexagonal NanoWire (NW) and NanoRing (NR) architectures, are introduced having higher current drivability and lower parasitic capacitance than conventional NW or NanoSlab devices. The standard cell sizing options, including a 1-fin-per-device version and a 2-fin-per-device design, are systematically evaluated. Each device flavor has multiple vertical stacks when wire-like or slab-like structure is used. Comprehensive transistor and logic cell studies demonstrate that the novel NR is the optimal structure for N5 and beyond.

Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM

Abstract: The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.

Fabrication of Vacuum-Sealed Capacitive Micromachined Ultrasonic Transducers With Through-Glass-Via Interconnects Using Anodic Bonding

Abstract: This paper presents a novel fabrication method for vacuum-sealed capacitive micromachined ultrasonic transducer (CMUT) arrays that are amenable to 3D integration. This paper demonstrates that MEMS structures can be directly built on a glass substrate with preformed through-glass-via (TGV) interconnects. The key feature of this new approach is the combination of copper through-glass interconnects with a vibrating silicon-plate structure suspended over a vacuum-sealed cavity by using anodic bonding. This method simplifies the overall fabrication process for CMUTs with through-wafer interconnects by eliminating the need for an insulating lining for vias or isolation trenches that are often employed for implementing through-wafer interconnects in silicon. Anodic bonding is a low-temperature bonding technique that tolerates high surface roughness. Fabrication of CMUTs on a glass substrate and use of copper-filled vias as interconnects reduce the parasitic interconnect capacitance and resistance, and improve device performance and reliability. A 16×16-element 2D CMUT array has been successfully fabricated. The fabricated device performs as the finite-element and equivalent circuit models predict. A TGV interconnect shows a 2-Ω parasitic resistance and a 20-fF shunt parasitic capacitance for 250-μm via pitch. A critical achievement presented in this paper is the sealing of the CMUT cavities in vacuum using a PECVD silicon nitride layer. By mechanically isolating the via structure from the active cells, vacuum sealing can be ensured even when hermetic sealing of the via is compromised. Vacuum sealing is confirmed by measuring the deflection of the edge-clamped thin plate of a CMUT cell under atmospheric pressure. The resonance frequency of an 8-cell 2D array element with 78-μm diameter circular cells and a 1.5-μm plate thickness is measured as 3.32 MHz at 15-V dc voltage (80% V pull-in ). [2016-0200].

On the Effect of Disorder on Stray Capacitance of Transformer Winding in High-Voltage Power Supplies

Abstract: Stray capacitance of transformer winding is an important parasitic element influencing the behavior of the switching power converters, especially for high-voltage transformers. There are various methods for calculating the stray capacitance in transformers and inductors with ordered windings. However, an ordered winding is less likely with an increased number of turns and layers. In this paper, it is shown that a slight disorderliness in winding leads to a considerable difference between the value of winding stray capacitance of the former ordered winding and its slightly disordered scheme. Therefore, regular methods for calculating the stray capacitance have significant errors in a disordered winding. A generic method is proposed to calculate the stray capacitance of a winding with disordered turns. The proposed method is to apply the probabilistic tools to evaluate the possible position of winding turns and calculation of stray capacitance for all possible winding diagrams. As the number of possible winding diagrams is very large, especially in high turn windings, Kolmogorov–Smirnov theorem is used to estimate the winding stray capacitance based on the reduced number of possible winding diagrams. The energy method is used to calculate the equivalent stray capacitance of winding. Using this calculation method, the effect of disorder and some other parameters on the value of stray capacitance is investigated. The proposed method is tested and validated with the computer simulation and the experimental measurement.

A Mathematical Model for Self-Priming Circuits: Getting the Most From a Dielectric Elastomer Generator

Abstract: A dielectric elastomer generator (DEG) can be used for converting mechanical energy from natural motion sources, such as walking, waves, trees, etc., into electrical energy. A DEG is comprised of a soft and flexible dielectric elastomer (DE) capacitor, a priming circuit (PC), which transfers high potential charge onto/off the DE electrodes, and a power extraction circuit that harvests the generated power. To generate power, the PC must charge and discharge the DE in synchronization with the DE's capacitance change. A simple circuit to do this exists: the self-priming circuit (SPC). The SPC consists of diodes and capacitors that passively switch between charge delivery and charge receiving states in synchronization with the DE's capacitance change. Until now, there has been no understanding of how to design an SPC in order to maximize harvested energy from the DE. A new mathematical model for an SPC is presented, leading to design and optimization. An accuracy of 0.1% between model, simulation, and experiment over five cycles is obtained, once losses are taken into consideration. The behavior of the SPC is shown to be related to the maximum and minimum capacitances of the DE, but is unaffected by the exact shape of the capacitance waveform.

A Reconfigurable Dual-Frequency Narrowband CMOS LNA Using Phase-Change RF Switches

Abstract: This paper presents a dual-band low-noise amplifier (LNA) that can be reversibly configured between 3 and 5 GHz using a phase-change (PC) RF switch. Simultaneous noise and conjugate input matching is achieved at the two frequencies using a single PC RF switch and coupled source inductors, thereby minimizing integration complexity and enabling a compact design roughly equal in size to a single-band design. The PC switch has extremely low on-state resistance (1.5– $4\Omega$ ) and parasitic capacitance (12–16 fF), and has a compact footprint ( $\sim 50~\mu \text{m}^{2}$ ). A chip containing the PC switch is fabricated in-house while the rest of the LNA is fabricated in a 0.13- $\mu \text{m}$ CMOS technology. The two chips are combined using an in-house flip-chip integration process. Characterization from five prototypes fabricated in two batches is presented. The integrated LNAs achieved peak gain greater than 20 dB and minimum noise figure less than 2.9 dB in both the frequency bands while consuming a peak power of 7.2 mW from a 1.2-V supply. Comparison of the CMOS-PC prototypes with carefully designed control LNAs demonstrates the effectiveness of the PC switch for RF reconfiguration, which allows the reconfigurable LNA to achieve performance comparable to its nonreconfigurable counterparts.

On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

Abstract: The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.

A new technique based on current measurement for nanoscale ferroelectricity assessment: Nano-positive up negative down.

Abstract: In this paper, we propose a new procedure which aims at measuring the polarisation switching current at the nanoscale on ferroelectric thin films with the atomic force microscope tip used as a top electrode. Our technique is an adaptation of the so-called positive up negative down method commonly operated on large electrodes. The main obstacle that must be overcome to implement such measurement is the enhancement of the signal to noise ratio, in a context where the stray capacitance of the sample/tip/lever/lever holder system generates a dielectric displacement current several orders of magnitude higher than the current to be measured. This problem is solved by the subtraction of the displacement current through a reference capacitance. For the first time, we show an example of nanoscale positive up negative down measurement of the polarisation charge on a PbZrTiO3 thin film and compare the measured value with paraelectric samples. From the comparison with macroscopic measurement, we deduce the effective area of contact between the tip and the sample.