Showing papers on "Parasitic capacitance published in 2019"
TL;DR: In this paper, a state-of-the-art 325 A, 1700 V SiC mosfet module has been fully characterized under various load currents, bus voltages, and gate resistors to reveal their switching capability.
Abstract: The higher voltage blocking capability and faster switching speed of silicon-carbide (SiC) mosfet s have the potential to replace Si insulated gate bipolar transistors (IGBTs) in medium-/low-voltage and high-power applications. In this paper, a state-of-the-art commercially available 325 A, 1700 V SiC mosfet module has been fully characterized under various load currents, bus voltages, and gate resistors to reveal their switching capability. Meanwhile, Si IGBT modules with similar power ratings are also tested under the same conditions. From the test results, several interesting points have been obtained: different to the Si IGBT module, the over-shoot current of the SiC mosfet module increases linearly with the increase of the load current and it has been explained by a model of the over-shoot current proposed in this paper; the induced negative gate voltage due to the complementary device turn- off (crosstalk effect) is more harmful to the SiC mosfet module than the induced positive gate voltage during turn- on when the gate off-voltage is –6 V; the maximum dv / dt and di / dt (electromagnetic interference) during switching transients of the SiC mosfet module are close to those of the Si IGBT module when the gate resistance is larger than 8 Ω but the switching loss of the SiC mosfet module is much smaller; the switching losses of the Si IGBT module are greater than those of the SiC mosfet module even when the gate resistance of the former is reduced to zero. An accurate power loss model, which is suitable for a three-phase two-level converter based on SiC mosfet modules considering the power loss of the parasitic capacitance, has been presented and verified in this paper. From the model, a 96.2% efficiency can be achieved at the switching frequency of 80 kHz and the power of 100 kW.
218 citations
TL;DR: The main features of the integrated inverter are: first, the leakage current caused by the solar cell array-to-ground parasitic capacitance can be theoretically reduced to zero due to the characteristics of the converter configuration, which can improve the efficiency and the reliability of the PV generation system.
Abstract: In this paper, an integrated step-up inverter without transformer is investigated for photovoltaic (PV) power generation. The proposed topology can be derived by combining a traditional boost converter with a single-phase full bridge dc–ac converter. The main features of the integrated inverter are: First, the leakage current caused by the solar cell array-to-ground parasitic capacitance can be theoretically reduced to zero due to the characteristics of the converter configuration, which can improve the efficiency and the reliability of the PV generation system; second, the output ac voltage of the proposed inverter can be higher than the input dc voltage, which is capable of connecting low voltage PV panels to the grid; third, only five active switches are used in the presented inverter, and those switching devices can be synchronously driven by various sinusoidal pulsewidth modulation methods based on the carrier; therefore, the proposed inverter is compact and with curtailed cost. The working principle and analysis of the proposed integrated inverter are elaborated. Finally, simulation and experimental results are obtained in a lab prototype, which agree well with the theoretical analysis.
105 citations
TL;DR: The findings not only establish an optimization methodology for the output performance of TENGs but also provide an insight into the process of triboelectrification.
Abstract: A triboelectric nanogenerator (TENG) is a potential solution for providing high output power by continuously harvesting ambient energy, which is expected to sustainably charge a battery for the new era—the era of the Internet of things and sensor networks. Generally, the existence of parasitic capacitance has been considered to be harmful in its output performance. Here, we systematically investigate the effects of structure and dimension of a TENG on its performance from the point view of parasitic capacitance by fabricating two types of layered TENGs with considering the dissimilarity of the two dielectric materials, symmetrical (ABBA) and alternate (ABAB) layered structure (SYM-TENG and ALT-TENG). Theoretical models of the two types of layered TENGs are proposed for illustrating their differences in parasitic capacitances and output characteristics. Larger parasitic capacitance enables the TENG to accommodate higher triboelectric charge density while reducing the internal impedance and maximum power de...
78 citations
TL;DR: In this article, an improved analytical stray capacitance model for inductors is proposed, which considers the capacitances between the winding and the central limb, side limb, and yoke of the core.
Abstract: This paper proposes an improved analytical stray capacitance model for inductors. It considers the capacitances between the winding and the central limb, side limb, and yoke of the core. The latter two account for a significant proportion of the total capacitance with the increase of the core window utilization factor. The potential of the floating core/shield is derived analytically, which enables the model to apply not only for the grounded core/shield, but also for the floating core/shield cases. On the basis of the improved model, an analytical optimization method for the stray capacitance in inductors is proposed. Moreover, a global Pareto optimization is carried out to identify the tradeoffs between the stray capacitance and ac resistance in the winding design. Finally, the analysis and design are verified by finite element method simulations and experimental results on a 100-kHz dual active bridge converter.
59 citations
TL;DR: In this article, the RF and DC characteristics of AlGaN/GaN High electron mobility transistor are analyzed using discrete field plate technique, which reduces the device parasitic capacitance exhibiting very low CGS and CGD.
Abstract: In this paper, the RF and DC characteristics of AlGaN/GaN High electron mobility transistor is analysed using discrete field plate technique. Surprisingly, it reduces the device parasitic capacitance exhibiting very low CGS and CGD of 5.8 × 10−13 F/mm and 4.2 × 10−13 F/mm respectively to improve the cut off frequency (fT) from 17.5 GHz to 20 GHz. The discrete field plate suppresses the maximum electric field between gate and drain region to achieve the high breakdown voltage of 330 V. The maximum transconductance (gm) achieved is 275 mS/mm, ensuring the better DC operation of the device. The simulated results clearly show that, the discrete field plate HEMTs are superior in performance over conventional GaN FP-HEMTs for future high frequency and high power applications.
47 citations
TL;DR: The proposed carrier-based discontinuous space-vector modulation (CB-DSVM) method with varying clamped area has comparative neutral-point voltage balancing ability and better input current quality.
Abstract: The three-level Vienna rectifier is an attractive topology for power factor correction applications. However, for practical high-frequency applications, the nonlinearity caused by snubber circuit and parasitic capacitance of Vienna rectifier's switching device will distort input current. This paper proposes a carrier-based discontinuous space-vector modulation (CB-DSVM) method with varying clamped area for Vienna rectifier in high switching frequency applications. The equivalent circuit of Vienna rectifier considering the nonlinear factors is built and the effect of pulse shaping around current zero-crossing point is investigated. The voltage errors caused by the nonlinearity of switching device will distort terminal voltage, which mainly appears at the zero-crossing time. A DSVM method with the fixed clamped area around the zero-crossing point is proposed to reduce the voltage errors and then the simplified CB-DSVM method with varying clamped area by adding a clamped factor to the judging conditions is further studied, which will reduce low-order harmonics of the CB-DSVM method. Simulations and experiments are carried out in a 600 W Vienna rectifier platform, which demonstrates the validity of the proposed method. Compared with the CB-SVM method, the proposed CB-DSVM method with varying clamped area has comparative neutral-point voltage balancing ability and better input current quality.
45 citations
TL;DR: In this paper, the authors review state-of-the-art applications of high-bandwidth conductance recordings of both ion channels and solid-state nanopores and show the potential for providing new insights into structure-function relations of these ion-channel proteins as the temporal resolutions of functional recordings matches time scales achievable with state of the art molecular dynamics simulations.
40 citations
TL;DR: Global modeling, simulation, and measurement results demonstrate that the PHE is limited by PCB/package parasitic capacitance and that PCB/packaging technology improvement to reduce parasitic capacitate by 150 fF could boost thePHE up to 45% for a low incident RF power level of −10 dBm.
Abstract: Simultaneous wireless information and power transfer (SWIPT) is a flexible and cheap way to supply Internet-of-Things (IoT) smart sensors avoiding battery replacement. In this paper, we analyze, model, and design a 2.45-GHz RF energy harvesting (RFEH) system based on a discrete-component matching network (MN), a custom 65-nm CMOS cross-coupled rectifier, and an off-the-shelf storage-charging power management unit (PMU), which regulates the rectifier output voltage with maximum power point tracking (MPPT). We propose a reverse global analysis to model the RFEH. It allows an accurate prediction of the power harvesting efficiency (PHE) to directly size the MN and select the RFEH MPPT regulation ratio, at different incident RF power levels. We perform parasitic-aware RFEH design to take advantage of printed circuit board (PCB)/package capacitive parasitics at the rectifier input for optimizing the $\pi $ -MN with the help of the proposed RFEH modeling results. We show that this parasitic capacitance introduces a maximum bound on the real impedance at the rectifier input to ensure good impedance matching in practice. MPPT is used to help reach this target real impedance at given incident RF power, as the rectifier equivalent input impedance is a function of both its input and output voltages. Measurement results show a sensitivity as low as −17.1 dBm with a peak PHE of 48.3% at −3-dBm incident RF power. Global modeling, simulation, and measurement results demonstrate that the PHE is limited by PCB/package parasitic capacitance and that PCB/packaging technology improvement to reduce parasitic capacitance by 150 fF could boost the PHE up to 45% for a low incident RF power level of −10 dBm.
35 citations
01 Jan 2019
TL;DR: In this article, the authors used junctionless transistors for the manufacturing of vertically stacked gate-all-around complementary FETs (CFETs) to reduce the number of lithographic steps required.
Abstract: For the first time, CMOS inverters and 6T-SRAM cells based on vertically stacked gate-all-around complementary FETs (CFETs) are experimentally demonstrated. Manufacturing difficulties of vertically stacked source and drain electrodes of the CFETs have been overcome by using junctionless transistors, thereby reducing the number of lithographic steps required. Furthermore, with post metallization treatments, both the voltage transfer characteristics (VTCs) of CMOS inverters and butterfly curves of SRAM show significant improvements due to the symmetry of nMOS and pMOS threshold voltages. Simulation shows that 3-dimensional CFET inverters have lower input parasitic capacitance than standard 2-dimensional CMOS, leading to reduced gate delay and lower power consumption.
34 citations
TL;DR: In this paper, an integrated, dual-output gate-drive power supply for gallium-nitride (GaN) 650-V, 60-A, half-bridge phase legs, rated at 2 W (2 × 1 W), 15 to 2 × 7 V, featuring an ultralow $C_{i}$ of 1.6 pF, a power density of 72 W/in3, and an efficiency of 85%.
Abstract: Wide-bandgap devices have been widely used to reduce the size and increase the efficiency of power converters by operating at a high switching frequency, at the expense of heightened radiated and conducted electromagnetic inference (EMI) emissions, of which the latter circulates through the power loop and ancillary circuitry. In effect, the parasitic isolation capacitance $C_{i}$ of the gate-driver power supply represents a key EMI propagation path to be controlled in order to ensure the operational integrity of power converters. To this end, this paper proposes an integrated, dual-output gate-drive power supply for gallium-nitride (GaN) 650 V, 60 A, half-bridge phase legs, rated at 2 W (2 × 1 W), 15 to 2 × 7 V, featuring an ultralow $C_{i}$ of 1.6 pF, an output-to-output parasitic capacitance of 1.6 pF, a power density of 72 W/in3, and an efficiency of 85%. All this is attained using an active-clamp flyback converter switching at 1 MHz using 65 V GaN high-electron-mobility transistor devices and Schottky output rectifiers, and a Pareto-optimized transformer design minimizing its interwinding capacitances, volume, and losses. Finally, the transformer is fully embedded in a printed circuit board (PCB) material, doubling as a substrate for the topside active layer of the power supply. The paper presents the complete design procedure, processing, and experimental demonstration of the proposed integrated power supply, evaluating as well the reliability impact of the magnetic-PCB material interface in high ambient temperature applications (>200 °C).
33 citations
TL;DR: In this paper, an all-film-capacitor, transformerless single-phase inverter for PV application is proposed, which is a combination of a front-end boost stage, a half-bridge (HB) inverter stage, and a buck-boost power decoupling stage.
Abstract: Photovoltaic (PV) inverters form the backbone of PV generation. This paper proposes an all-film-capacitor, transformerless single-phase inverter for PV application. The topology is a combination of a front-end boost stage, a half-bridge (HB) inverter stage, and a buck–boost power decoupling stage. The grid ripple power is decoupled by a large swing of the HB capacitors along with a limited ripple on the dc link, thus reducing the capacitance requirement and converter volume. Being an HB-derived inverter, the high-frequency common mode leakage current through the PV parasitic capacitance is mitigated. Furthermore, the dc-link average is optimally controlled to ensure a higher efficiency over wide operating load and power factor range. To validate its operation, a Silicon Carbide based 1-kVA laboratory prototype is built and closed-loop experimental results are provided at 100/75 kHz switching frequency over wide operating conditions.
TL;DR: The proposed partially interleaved structure features lower leakage inductance, smaller AC capacitance and lower rate of AC-DC resistance, which is suitable for high-frequency high-efficiency applications.
Abstract: This paper proposes an improved partially interleaved structure for high-voltage (several kV) high-frequency (several hundred kHz) multiple-output applications. The proposed transformer structure is compared with other typical structures with the leakage inductance, ac capacitance, ac resistance, and the ratio of ac–dc resistance taken into consideration. The proposed structure features lower leakage inductance, smaller ac capacitance, lower ac resistance, and lower ratio of ac–dc resistance, which is suitable for high-frequency high-efficiency applications. A planar transformer with the proposed structure was built and tested in an LCLC resonant converter, where the input voltage is 40 V, the output is 4800 V, the switching frequency is 500 kHz, the output power is 288 W, and the efficiency is 96.8%, which validates the analysis.
06 Mar 2019
TL;DR: This work presents a Gm-R based RA which has a complete-settled amplification characteristic, thus allowing us to compensate the gain variation over temperature easily with a tracking bias technique and uses a two-stage amplification to alleviate the RA input parasitic capacitance that enables a small DAC size in all stages.
Abstract: Continuous technology scaling has allowed unceasing growth of the sampling rate of a single channel ADC in past decades. Such development not only helps reduce the number of channels in massively time interleaved ADCs, but also contributes to lower their overall jitter and input capacitance, thus enabling a further push on the ADC performance boundary. Being limited by metastability, the conventional SAR architecture is not suitable when both high resolution and speed are essential. While the pipeline SAR offers a higher speed alternative, it also keeps the low and dynamic power nature of the SAR architecture through adopting dynamic or integrating residue amplifiers (RAs) in recent works [1, 2]. With an integrating characteristic, the amplification time can be short but in contrast, the linearity, extra reset time of the load, and PVT sensitivity pose significant design challenges. In this work, rather than adopting the integratingtype amplifier, we present a Gm-R based RA which has a complete-settled amplification characteristic, thus allowing us to compensate the gain variation over temperature easily with a tracking bias technique. Besides this, we use a two-stage amplification to alleviate the RA input parasitic capacitance that enables a small DAC size in all stages. The single channel prototype reaches 1GS/s with 60.02dB SNDR at a Nyquist input consuming 7.6mW from a 1V supply.
01 Sep 2019
TL;DR: In this paper, a 5-level MMC based transformerless dc/ac converter is developed for 13.8 kV medium voltage grid using 10 kV SiC MOSFETs.
Abstract: Medium voltage (MV) power converters using high voltage (HV) Silicon Carbide (SiC) power semiconductors result in great benefits in weight, size, efficiency and control bandwidth. However, challenges still exist on the components design considering HV insulation and noise immunity requirements in the MV SiC based power converter. A 5-level MMC based transformer-less grid-connected dc/ac converter is developed for 13.8 kV medium voltage grid using 10 kV SiC MOSFETs. The key components, including gate driver with high dv/dt immunity and fast reliable protection, isolated power supply with low parasitic capacitance, voltage/current sensors with high noise immunity, and passives following related insulation standard are provided. A 25 kV dc-link phase-leg is demonstrated, and the experimental results are presented.
TL;DR: This paper presents a touch sensing analog front end (AFE) for capacitive touch-screen integrated into an ultra-thin display that exhibits a power reduction of 64% due to the adiabatic driving method.
Abstract: This paper presents a touch sensing analog front end (AFE) for capacitive touch-screen integrated into an ultra-thin display. Reduced distance between the touch screen and display causes large capacitive coupling, resulting in increased parasitic capacitance and reduced touch sensitivity. Display noise interference is worse due to the large coupling capacitance. Hence, it is a challenge to design an AFE capable of accurate and energy efficient sensing of a touch input in the integrated touch-screen panel. An adiabatic multi-driving method based on charge recycling is proposed to provide power-efficient stimulation of the touch-screen panel. Furthermore, in order to cancel out the display noise interference through the large parasitic capacitance, a fully differential touch sensing module is incorporated in the AFE. A correlated noise sampling (NS) is employed in the decoder stage for the multi-driving demodulation process. To further improve power efficiency, the sensing module is multiplexed in four ways while achieving an optimal conversion time per sample. The proposed AFE was implemented in a 180-nm CMOS process. The fabricated AFE shows 57.0-dB signal-to-noise ratio (SNR) at 120 fps while consuming 17.8 mW. Compared with power consumption of 19.9 mW expected with a conventional signal generation, the proposed adiabatic signal generator dissipates only 7.1 mW, exhibiting a power reduction of 64% due to the adiabatic driving method.
TL;DR: In this paper, a 1-kV input SiC LLC converter with matrix planar transformers is proposed to achieve high efficiency and high power density with a split resonant tank for high input voltage applications.
Abstract: A 1-kV input SiC LLC converter with the matrix planar transformers is proposed to achieve high efficiency and high power density. With fast switching speed 140 ns of SiC mosfet s at 1-kV input voltage, high dv/dt of 11.8 kV/ μ s can cause large displacement current via the parasitic capacitance between the primary and secondary sides of high-frequency planar transformers. The displacement current via the interwinding capacitance can distort the resonant current seriously. This causes the control mosfet s not to realize ZVS and induces high switching loss at 1 kV. An LLC topology with split resonant tanks is proposed for high input voltage applications. The resonant tank is split into two identical resonant tanks to provide symmetrical resonant current with the same impedance. Compared with the conventional LLC converters, the input and output current of the resonant tank is symmetrical, avoiding the current distortion. Therefore, all of the control mosfet s can realize ZVS. The transformer interwinding capacitance modeling and a reduction solution are presented, which reduces the waveform distortion by 68%. Two SiC prototypes of 3 and 4 kW with an input of 1 kV and output of 32 and 48 V were built, respectively. The efficiency is 94.9% at full load at 300 kHz for a 3-kW module and 96.0% at full load for a 4-kW module. The power density is 3.87 kW/L (63.4 W/in3) and 4.11 kW/kg for the 4-kW module.
TL;DR: A systematic approach for self-capacitive fingerprint sensor integrating Al-InSnZnO TFTs with field-effect mobility higher than 30 cm2/Vs, which enable isolation between pixels, by employing industry-friendly process methods.
Abstract: The fingerprint recognition has been widely used for biometrics in mobile devices. Existing fingerprint sensors have already been commercialized in the field of mobile devices using primarily Si-based technologies. Recently, mutual-capacitive fingerprint sensors have been developed to lower production costs and expand the range of application using thin-film technologies. However, since the mutual-capacitive method detects the change of mutual capacitance, it has high ratio of parasitic capacitance to ridge-to-valley capacitance, resulting in low sensitivity, compared to the self-capacitive method. In order to demonstrate the self-capacitive fingerprint sensor, a switching device such as a transistor should be integrated in each pixel, which reduces a complexity of electrode configuration and sensing circuits. The oxide thin-film transistor (TFT) can be a good candidate as a switching device for the self-capacitive fingerprint sensor. In this work, we report a systematic approach for self-capacitive fingerprint sensor integrating Al-InSnZnO TFTs with field-effect mobility higher than 30 cm2/Vs, which enable isolation between pixels, by employing industry-friendly process methods. The fingerprint sensors are designed to reduce parasitic resistance and capacitance in terms of the entire system. The excellent uniformity and low leakage current (<10−12) of the oxide TFTs allow successful capture of a fingerprint image.
TL;DR: With increasing penetration of renewable energy sources into distributed power systems, multi-parallel inverters are commonly employed in the interface to the utility grid, giving rise to potential resonance problems, according to this issue common-mode resonance of single inverter and multi- parallel inverter are analyzed.
Abstract: With increasing penetration of renewable energy sources into distributed power systems, multi-parallel inverters are commonly employed in the interface to the utility grid, giving rise to potential resonance problems. Aiming at this issue, common-mode resonance of single inverter and multi-parallel inverters are analyzed. First, single inverter common-mode circuits model is built. Common-mode paths are found in it and the admittances of each path are analyzed. Based on it, multi-parallel inverters equivalent circuits are modeled and analyzed. In order to investigate common-mode resonance characteristics, self-coupled and mutual-coupled paths are analyzed and compared to single inverter's path. To get more accuracy resonance characteristics, a crossover filter function is introduced and used to separate output common-mode currents at different frequencies for two-parallel inverters. The impact of parasitic capacitance on resonance is examined. Experimental results validate the developed models and the proposed resonance characteristics.
TL;DR: In this paper, the authors proposed and fabricated resonant-tunneling-diode (RTD) terahertz oscillators integrated with a cylindrical cavity.
Abstract: We proposed and fabricated resonant-tunneling-diode (RTD) terahertz oscillators integrated with a cylindrical cavity. Oscillation frequency of 3 THz is expected from theoretical analysis. As a preliminary experiment, the proposed oscillator was fabricated using electron-beam lithography with a three-layer-resist process. An oscillation of up to 1.79 THz was obtained in the fabricated oscillators, which was lower than the theoretical expectation. This was because of a parasitic capacitance of the metal post connecting the cavity and the RTD. Theoretical calculations, including this parasitic capacitance, agreed well with the experiment. The parasitic capacitance can be suppressed by adding a simple process to the cavity fabrication.
TL;DR: In this paper, a 3D additive manufacturing technique was used to fabricate high-frequency, tapered-solenoid type inductors for RF applications capable of wide bandwidth performance.
Abstract: The capability to additively manufacture fully-functioning electronic circuits is a frontier in 3D-printed electronics that will afford unprecedented scalability, miniaturization, and conformability of electronic circuits. The printed passives, such as resistors, capacitors, and inductors, however, are rarely capable of performances comparable to that of the commercially available versions. In this paper, we report a novel procedure that employs three-dimensional (3D) additive manufacturing techniques to fabricate high-frequency, tapered-solenoid type inductors for RF applications capable of wide bandwidth performance. The design includes a polymer support structure to reduce the parasitic capacitance between the inductor and the substrate, a tapered solid core, and conducting windings. Each design component is printed using aerosol-jet (AJ) printing methods on a grounded coplanar waveguide such that the small end of the conical-shaped inductor is connected to the transmission line and the base of the inductor is connected to ground. Two types of solid-core inductors were fabricated: one with a printed polymer core and another with a non-printed iron core. Scattering parameter measurements establish that the polymer and iron-core inductors, combined with a 45°-polymer support structure, can achieve usable bandwidths up to 18 GHz and 40 GHz, respectively, with low insertion loss. 3D model and circuit model simulations were also carried out to study inductor performance in terms of self-resonance and insertion loss.
TL;DR: In this article, a wideband differential low-noise amplifier (LNA) for multiband wireless communication applications is proposed, where shunt peaking is implemented with a self-biased active inductor (AI) to realize wideband characteristics in a compact size.
Abstract: In this article, a wideband differential low-noise amplifier (LNA) for multiband wireless communication applications is proposed. First, shunt peaking is implemented with a self-biased active inductor (AI) to realize wideband characteristics in a compact size. Second, a cross-coupled capacitor is added to the AI, thus constructing a feedforward path. It adds a signal to the output node so that the bandwidth (BW) can be further increased by compensating the gain reduction according to the frequency. Additionally, the feedforward path creates another feedback loop, generating a negative capacitance. The negative capacitance can cancel parasitic capacitance to increase BW with a cascade amplifier. The prototype LNA is fabricated with a 65-nm CMOS process. It has a gain of 26.7 dB and a BW of 4.1 GHz. The noise figure (NF) is 3 dB and the third-order input intercept point (IIP3) is −14.2 dBm at 2 GHz. It consumes 13.9 mA at a 1-V supply and has an area of 0.009 mm2.
TL;DR: In this paper, a linear-array receiver analog front-end (AFE) circuit, which mainly consists of 16 transimpedance amplifiers (TIAs), is presented for pulsed time-of-flight (TOF) rotating scanner light detection and ranging (LiDAR) application.
Abstract: A linear-array receiver analog front-end (AFE) circuit, which mainly consists of 16 transimpedance amplifiers (TIAs), is presented for pulsed time-of-flight (TOF) rotating scanner light detection and ranging (LiDAR) application. In particular, a single-channel TIA with a novel cascaded combination consists of a transimpedance preamplifier biased by a power supply of 1.8 V, a post amplifier (PA), and an output buffer (OB) with a 3.3-V power supply, aiming to lower the parasitic capacitance of the input stage and widen the output swing range, respectively. Meanwhile, the input-referred noise current is investigated to evaluate the detecting capability for the weak pulse current, and the crosstalk reduction schemes in circuit design and layout design are presented for the proposed AFE circuit. The proposed AFE circuit, which achieves a high gain of 100 dB ${\Omega }$ , a low gain of 60 dB ${\Omega }$ , a simulated transimpedance gain bandwidth of approximately 450 MHz, an equivalent input-referred noise current of 2.59 pA/Hz0.5, a signal-to-crosstalk ratio of 40.1 dB between adjacent channels, and a minimum detectable signal of $2.5~{\mu }\text{A}$ at SNR = 5, was fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS technology. The total area of AFE circuit, which includes the circuit core, bandgap and bias circuits, and I/O PAD, is approximately equal to ${4.80}\times {0.85}$ mm2.
TL;DR: In this paper, an appropriate ratio between the gate-drain capacitance and the common-source inductance is a key to prevent the oscillatory false triggering in GaN-FETs.
Abstract: Gallium-nitride-field-effect transistors (GaN-FETs) are promising switching devices with fast switching capability However, they commonly have low gate threshold voltage, suffering from susceptibility to the false triggering Particularly, the oscillatory false triggering, ie, a self-sustaining repetitive false triggering, can occur after a fast switching, which is a severe obstacle for industrial applications The purpose of this paper is to elucidate the design instruction for preventing this phenomenon The oscillatory false triggering is known to be caused by the parasitic oscillator circuit formed of a GaN-FET, its parasitic capacitance and the parasitic inductance of the wiring This paper analyzed the nonoscillatory condition of this oscillator The result revealed an appropriate ratio between the gate-drain capacitance and the common-source inductance is a key to prevent the oscillatory false triggering Experiment successfully verified this analysis result, supporting the effectiveness of the appropriate design of this ratio for preventing the oscillatory false triggering
TL;DR: This review summarizes practical solutions that can mitigate the impact of nonideal device and circuit properties of resistive memory by static parameter and dynamic runtime co-optimization and portrays an unified reconfigurable computational memory architecture.
Abstract: Emerging computational resistive memory is promising to overcome the challenges of scalability and energy efficiency that DRAM faces and also break through the memory wall bottleneck. However, cell-level and array-level nonideal properties of resistive memory significantly degrade the reliability, performance, accuracy, and energy efficiency during memory access and analog computation. Cell-level nonidealities include nonlinearity, asymmetry, and variability. Array-level nonidealities include interconnect resistance, parasitic capacitance, and sneak current. This review summarizes practical solutions that can mitigate the impact of nonideal device and circuit properties of resistive memory. First, we introduce several typical resistive memory devices with focus on their switching modes and characteristics. Second, we review resistive memory cells and memory array structures, including 1T1R, 1R, 1S1R, 1TnR, and CMOL. We also overview three-dimensional (3D) cross-point arrays and their structural properties. Third, we analyze the impact of nonideal device and circuit properties during memory access and analog arithmetic operations with focus on dot-product and matrix-vector multiplication. Fourth, we discuss the methods that can mitigate these nonideal properties by static parameter and dynamic runtime co-optimization from the viewpoint of device and circuit interaction. Here, dynamic runtime operation schemes include line connection, voltage bias, logical-to-physical mapping, read reference setting, and switching mode reconfiguration. Then, we highlight challenges on multilevel cell cross-point arrays and 3D cross-point arrays during these operations. Finally, we investigate design considerations of memory array peripheral circuits. We also portray an unified reconfigurable computational memory architecture.
02 Jun 2019
TL;DR: In this article, a Doherty power amplifier architecture with impedance inverting balun and impedance scaling balun is proposed to support Doherty active load modulation and power back-off (PBO) efficiency enhancement at high mm-wave frequencies.
Abstract: We propose a Doherty power amplifier architecture with impedance inverting balun and impedance scaling balun to support Doherty active load modulation and Power Back-Off (PBO) efficiency enhancement at high mm-Wave frequencies. Unlike transformer baluns often used at RF frequencies, mm-Wave coupler-based baluns are employed to provide well balanced differential-to-single-ended conversion and absorb device output parasitic capacitance. Moreover, this paper reports that coupler-based balun with 45° electrical length exhibits impedance inverting behavior, which is utilized to construct Doherty active load modulation network in the reported PA design. Adaptive biasing circuit further enhances the Main/Auxiliary PA cooperation. The measured Doherty PA exhibits 20.1dBm P sat , 19.3dBm P 1dB , and 26% peak PAE. At 7dB PBO, the measured PAE is 16.6%, demonstrating 1.45× efficiency enhancement compared to an ideal class-B PA with the same peak PAE at P 1dB .
TL;DR: In this paper, a low-power CMOS digitally controlled variable gain low-noise amplifier (VGLNA) at the $V$ -band in a 40-nm LP CMOS process is presented.
Abstract: This article presents a low-power CMOS digitally controlled variable gain low-noise amplifier (VGLNA) at $V$ -band in a 40-nm LP CMOS process. There are three amplifier stages and three digital gain control bits in this VGLNA. The first stage is a common source amplifier, and the second and third stages are current-reused amplifiers. In order to save dc power and control gain, we use the current-reused technique and add the digital switch between upper and lower transistors. Due to constant dc current, the input impedance of the current-reused stage is stable. Output impedance is stabilized by an ac grounding capacitor at the source terminal of the upper transistor under gain switching. Thus, our proposed VGA can minimize the interstage influence with the previous and following stage and maintain OP1dB due to the constant bias current. By adding a resonated inductor to cancel out the parasitic capacitance of switch transistor, we can keep bandwidth and improve noise figure (N.F.) at the current-reused stages under different gain states. The measured peak gain is 19.8 dB at 59.6 GHz, and lowest N.F. is 5.98 at 63.5 GHz. The gain states are 19.8/15.3/11.5/6.5 dB, respectively, and the measured input/output return loss is stable under different gain states. The IP1dB is increased from −29.5 to −17 dBm, and the OP1dB is nearly constant under different gain states. Total dc power consumption is only 18 mW for 1.1-V supplied voltage. This is the first digital current-reused VGLNA that has good FoM among digital VGLNA, the lowest dc power consumption, and compact die area at $V$ -band.
TL;DR: In this article, two suppression methods by changing the stator winding-to-rotor and end-winding-torotor capacitances are proposed to mitigate the effect of stator wound to rotor capacitance coupling on the shaft-toframe voltage.
Abstract: Common-mode voltage by switching pattern of space vector pulsewidth modulation excites parasitic capacitance coupling in interior permanent magnet synchronous motors, and it finally causes a shaft-to-frame voltage. Among all parasitic capacitances, winding-to-rotor parasitic capacitance has the greatest effect on the shaft-to-frame voltage, which means the winding-to-rotor parasitic capacitance must be suppressed for noticeable mitigation of the shaft-to-frame voltage. This paper proposes two suppression methods by changing the stator winding-to-rotor and end winding-to-rotor capacitances. First, the modified winding shape is utilized for the suppression of stator winding-to-rotor capacitance. Second, a copper shield is applied to suppress the end winding-to-rotor parasitic capacitance. Finally, both the methods are applied together to mitigate the effect of the stator winding-to-rotor and end winding-to-rotor capacitances on the shaft-to-frame voltage.
TL;DR: A new bearing current suppression method in DFIGs is proposed based on the bearing voltage ratio and the results verify that the new suppression method can effectively suppress the bearing currents.
Abstract: Doubly-fed induction generators (DFIGs) are widely used in the wind power generation systems. However, due to the use of the power electronic devices, such as insulated gate bipolar transistor (IGBT), it is inevitable to generate a non-zero common mode voltage on the rotor side. The common mode voltage can induce the bearing voltage through the stray capacitances and result in the bearing currents, which seriously affect the efficiency and the safety of wind power generation system. This paper proposes a new bearing current suppression method in DFIGs. The key is to design the electrostatic shield on the rotor side of DFIGs and based on the bearing voltage ratio to effectively mitigate the bearing voltage ratio in the generator. This paper firstly investigates the bearing current equivalent circuit and the stray capacitance calculation method. The sensitivity analysis on the bearing voltage ratio is carried out, which shows that the capacitance between the rotor winding and the rotor core is a key parameter to mitigate the bearing voltage and bearing currents. The electrostatic shield on the rotor side of DFIGs is designed to regulate the capacitance value and hence the bearing currents. Finally, the bearing current of the converter-DFIG system is simulated and analyzed. The results verify that the new suppression method can effectively suppress the bearing currents.
17 Mar 2019
TL;DR: In this paper, two different scenarios of the zero-voltage switching (ZVS) condition for an LLC series resonant converter with secondary parasitic capacitance were presented, and the impact of the resonant to steady state operation under different ZVS timing was discussed.
Abstract: The LLC series resonant converter is widely used in many applications due to its high power density and efficiency. However, under applications with relatively small magnetizing current and resonant inductance such as DC transformer (DCX) for telecom power systems and PV optimizers, the resonance between the leakage inductance and the secondary parasitic capacitance during dead-time is unneglectable. It will affect the zero-voltage switching (ZVS) transition and the resonant current during the power delivery period. Therefore, in this paper, two different scenarios of the ZVS condition for an LLC series resonant converter with secondary parasitic capacitance considered will be presented. Moreover, the impact of the resonant to steady state operation under different ZVS timing will be discussed. Experimental results of a 140kHz prototype are provided for verification.
TL;DR: In this paper, a pixel circuit with high resolution and high luminance uniformity for organic light emitting diode-on-silicon (OLEDoS) microdisplays was proposed.
Abstract: This paper proposes a pixel circuit with high resolution and high luminance uniformity for organic light emitting diode-on-silicon (OLEDoS) microdisplays. The proposed pixel circuit employs a simple structure that consists of four n-channel MOSFETs and one capacitor, resulting in high resolution. In addition, this circuit compensates for the threshold voltage ( $V_{th}$ ) variation of the driving transistor caused by the body effect, which increases the $V_{th}$ as the source-to-body voltage of the driving transistor increases, thus reducing the emission current deviation, resulting in a high luminance uniformity. Moreover, the proposed pixel circuit extends the data voltage range using the capacitive coupling of the storage capacitance and the parasitic capacitance at the gate node of the driving transistor to precisely control the emission current. To verify the performance of the proposed pixel circuit, a test pattern with an array of the proposed 4T1C pixel circuits was fabricated on a single-crystalline silicon wafer as a backplane using a 110 nm standard CMOS process with 5.5 V high-voltage devices. The proposed pixel circuit occupies a unit sub-pixel area of $5.76 \mu \mathrm {m} \times 1.92 \mu \text{m}$ , which corresponds to a resolution of 4410 pixels per inch. The measurement results show that the emission current deviation error of the proposed pixel circuit ranges between −1.16% and +1.14%, which is improved from between −45.97% to +45.42% achieved in the conventional current-source type 2T1C pixel circuit, which does not compensate for the $V_{th}$ variation of the driving transistor. Moreover, the measured data voltage range of the proposed pixel circuit is extended to 1.618 V, which is 8.17 times wider than that of the conventional pixel circuit. Therefore, the proposed pixel circuit is very suitable for high resolution and high luminance uniformity of OLEDoS microdisplays.