Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

A 2.5Gb/s/ch 4PAM inductive-coupling transceiver for non-contact memory card

Abstract: An inductive-coupling link has been studied for inter-chip communications in System-in-a-Package [1]. Its communication distance extends millimeter ranges [2,3] and it can be used as a wireless interface for non-contact memory cards. High speed and low power communication can be performed in the inductive-coupling link because of the removal of highly capacitive ESD protection devices [1]. The wireless interface eliminates mechanical contacts resulting in high reliability. Target data rate is 2.5Gb/s/ch which is 12.5x higher than that of a commercial memory card and target communication range is 0.5mm to 1mm, considering the allowance of card insertion. The maximum data rate of the inductive-coupling link demonstrated in [3] at 1mm distance was 160Mb/s/ch. A theoretical limit is 1Gb/s/ch since self resonant frequency of an on-chip inductor of 3GHz. To increase the self resonant frequency, the inductor is moved off chip to a flexible circuit board to reduce parasitic capacitance. The self resonant frequency of 1mm diameter inductor is increased to 4GHz corresponding to a signal data rate of 1.25Gb/s/ch. Additionally, the number of bit per symbol is increased to 2 by 4 pulse amplitude modulation (4PAM) and a data rate of 2.5Gb/s/ch is achieved. But to communicate by using 4PAM in the inductive-coupling link, issues listed below must be solved. First, the communication range is limited to 0.95mm to 1mm. The amplitude of the received signal is inversely proportional to the communication distance, and therefore, received signal cannot be converted to a correct data without adjusting the input threshold voltages of a receiver. Second, the pulse width is narrower in 4PAM and thus synchronization on the receiver side is difficult.

3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS

Abstract: At data rates beyond 10Gb/s, most wireline links employ NRZ signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from process scaling in the same fashion that circuit design does. Reflections from impedance discontinuities in the PCB and package caused by vias and connectors introduce significant signal loss and distortions at higher frequencies. Even with an ideal channel, at every package-die interface, there is an intrinsic parasitic capacitance due to the pads and the ESD circuit amounting to at least 150fF, and a 50Ω resistor termination at both the transmit and receive ends resulting in an intrinsic pole at 23GHz or lower. In light of all these limitations, serial NRZ signaling beyond 60Gb/s appears suboptimal in terms of both power and performance. Utilizing various modulation techniques such as PAM4, one can achieve a higher spectral efficiency [2]. To enable such transmission formats, high-speed moderate-resolution data converters are required. This paper describes a 36Gb/s transmitter based on an 18GS/s 8b DAC implemented in 28nm CMOS, compliant to the new IEEE802.3bj standard for 100G Ethernet over backplane and copper cables [3].

10.2: Invited Paper: Development of Oxide TFT's Structures

Abstract: Advanced structures of oxide TFT have been studied for various display applications. Oxide TFT with etch-stopped layer has shown excellent uniformity and stability for display products. For mass production with low cost, however, back channel etched structure with/without titanium etch-stopped one has been studied and demonstrated promising electrical properties comparable to etch stop structure. Furthermore, we have developed self-aligned coplanar structure as one of ways to minimize parasitic capacitance and found excellent electrical properties and bias stability at 6 μm of channel length, which is demonstrated with 13.3 inch AMOLED.

Picture flicker improvable liquid crystal display device and relevant driving method thereof

Abstract: The invention provides a picture flicker improvable liquid crystal display device and a relevant driving method thereof. The method adjusts the chamfering amplitude of a grid driving signal to reduce The invention provides a picture flicker improvable liquid crystal display device and a relevant driving method thereof. The method adjusts the chamfering amplitude of a grid driving signal to reducetnce value of the first pixel is less than that of the second pixel, the first potential is higher than the second potential. The invention can effectively eliminate the picture flicker to improve theance value of the first pixel is less than that of the second pixel, the first potential is higher than the second potential. The invention can effectively eliminate the picture flicker to improve the display quality through adjusting the common voltage.display quality through adjusting the common voltage.he picture flicker and comprises the steps of respectively providing a first grid driving signal and a second grid driving signal according to parasitic capacitance values of a first pixel and a secothe picture flicker and comprises the steps of respectively providing a first grid driving signal and a second grid driving signal according to parasitic capacitance values of a first pixel and a second pixel. The first grid driving signal comprises a waveform descending edge descending from a high potential to a first potential, and the second grid driving signal comprises a waveform descending end pixel. The first grid driving signal comprises a waveform descending edge descending from a high potential to a first potential, and the second grid driving signal comprises a waveform descending edge descending from a high potential to a second potential; when the parasitic capacitance value of the first pixel is larger than that of the second pixel, the first potential is lower than the secondge descending from a high potential to a second potential; when the parasitic capacitance value of the first pixel is larger than that of the second pixel, the first potential is lower than the second potential; when the parasitic capacitance value is substantially equal to that of the second pixel, the first potential is substantially equal to the second potential; and when the parasitic capacitd potential; when the parasitic capacitance value is substantially equal to that of the second pixel, the first potential is substantially equal to the second potential; and when the parasitic capacita

Capacitance and Inductance Sensor Circuits for Detecting the Lengths of Open- and Short-Circuited Wires

Abstract: The length of an open- or short-circuited wire is linearly proportional to the capacitance or inductance of the wire, respectively. Several types of simple and inexpensive circuits are introduced to measure these values. Open-circuited (capacitance) measurements are very effective. Short-circuited (inductance) measurements are more difficult, and not all of the circuits worked well. A 555 timer circuit was found to have the best overall performance to locate the ends of both open- and short-circuited wires. The capacitance and inductance values of various types of aircraft wires were measured and verified with analytical equations.