Topic
Parasitic capacitance
About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.
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TL;DR: It is shown that if the stray capacitance varies between 90 and 210 pF, the measurement error would be between +0.03% to -0.1%.
Abstract: An ac-based capacitance transducer has been designed for use in electrical capacitance tomography (ECT) systems. The stray capacitance between the measurement electrodes and earth can be relatively large and may affect the performance of the transducer. This paper analyzes this effect, taking into account the ON-resistance of the CMOS switches in the circuit, the finite gain of op-amps and gain errors in the detection measuring unit, so that the overall measurement error can be estimated. It is shown that if the stray capacitance varies between 90 and 210 pF, the measurement error would be between +0.03% to -0.1%. This is negligibly small for ECT applications, confirming that this ac-based capacitance transducer is effectively stray-immune.
40 citations
TL;DR: The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor and an equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ ground noise in the time domain.
Abstract: The nonmonotonic behavior of power/ground noise with respect to the transition time tr is investigated for an inductive power distribution network with a decoupling capacitor. The worst case power/ground noise obtained with fast switching characteristics is shown to be significantly inaccurate. An equivalent transition time that corresponds to resonance is presented to accurately estimate the worst case power/ground noise in the time domain. Furthermore, the sensitivity of the ground noise to the decoupling capacitance Cd and parasitic inductance Lg is evaluated as a function of the transition time. Increasing the decoupling capacitance is shown to efficiently reduce the noise for transition times smaller than twice the LC time constant, tr les 2radic(LgCd). Alternatively, reducing the parasitic inductance Lg is shown to be effective for transition times greater than twice the LC time constant, tr ges 2radic(LgCd). The peak noise occurs when the transition time is approximately equal to twice the LC time constant, tr ap 2radic(LgCd) , referred to as the equivalent transition time for resonance.
40 citations
TL;DR: In this article, a semianalytical extrinsic gate capacitance model for silicon-on-insulator triple-gate FinFET, based on 3D numerical simulations, is presented.
Abstract: Triple-gate FinFETs have demonstrated to be promising candidates to push further the performance limits of the microelectronics industry, thanks to their high immunity to short-channel effects. However, owing to their 3-D nature, high parasitic gate capacitances appear that dramatically degrade their high-speed digital and analog/RF performances. Thus, in order to meet the International Technology Roadmap of Semiconductors projection, it is mandatory to find layout or technological solutions to reduce the total parasitic gate capacitance. In this context, it is necessary to develop a model that describes the parasitic capacitance in terms of the FinFET geometry. In this paper, a semianalytical extrinsic gate capacitance model for silicon-on-insulator triple-gate FinFET, based on 3-D numerical simulations, is presented. The model takes into account the external (five components) and internal (two components) fringing capacitances from the gate to the source/drain electrodes as well as the overlap capacitances. Comparisons with experimental results are presented to validate the developed model. Finally, based on the developed model, the evolution of the total parasitic gate capacitance as the channel length is reduced toward the 12-nm technology node is analyzed.
40 citations
TL;DR: In this paper, the authors review state-of-the-art applications of high-bandwidth conductance recordings of both ion channels and solid-state nanopores and show the potential for providing new insights into structure-function relations of these ion-channel proteins as the temporal resolutions of functional recordings matches time scales achievable with state of the art molecular dynamics simulations.
40 citations
Patent•
04 Jan 1989
TL;DR: In this paper, a linear capacitance displacement transducer for measuring absolute displacement is formed from a coaxial variable capacitor and a precision capacitance measuring electronic circuit, where the plates of the coaxial capacitor are attached to the members of an assembly whose displacement relative to one another is determined.
Abstract: A linear capacitance displacement transducer for measuring absolute displacement is formed from a coaxial variable capacitor and a precision capacitance measuring electronic circuit. The plates of the coaxial capacitor are attached to the members of an assembly whose displacement relative to one another is to be determined. Linear displacement of the members causes a linear displacement between the capacitor plates which is reflected in a linear capacitance change. A capacitor controlled oscillator utilizes the coaxial variable capacitor at its input. The capacitor controlled oscillator whose period of oscillation is been determined by the capacitance and locked in phase with changes of capacitance is utilized as a precision measure of capacitance. The period of the square wave output of the oscillator is a linear function of the capacitance of the variable capacitor at any time. The transducer may be adapted to determine the absolute position of a piston rod in a hydraulic cylinder.
40 citations