Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Electric circuit arrangement and method of making the same

Abstract: A circuit board of electrically insulating material is provided with a printed circuit including one or more circuit strips. A discrete electrical component, or several of them, is mounted on the circuit board in circuit with the circuit arrangement, and at least one semi-conductor unit is provided on the circuit board and electrically connected with the circuit thereof.

High-frequency negative-resistance circuit principles for Esaki-diode applications

Abstract: Certain fundamental principles are presented for analyzing and designing high-frequency amplifiers and oscillators utilizing simple negative resistance elements such as the Esaki or tunnel diodes. The first part of the paper covers the conditions necessary for oscillation and amplification with a single negative-resistance diode, including stability criteria, gain and bandwidth. It is shown that the highest-frequency circuits require diodes with very small dimensions, so that a single-spot diode will have a very low power capacity. In order to obtain higher power at high frequencies, distributed circuits must be used, either with narrow-strip diodes or a multiplicity of small spot diodes. Such circuits present special stabilization problems in suppressing unwanted modes of oscillation. Methods of avoiding such difficulties are presented for one-port oscillator circuits and for traveling-wave amplifier circuits. In the latter case, nonreciprocal attenuation of the gyromagnetic type is recommended.

Bipolar transistor-field effect transistor composite circuit

Abstract: A bipolar transistor-complementary field effect transistor composite circuit is provided which includes a pair of first and second bipolar transistors each having a collector of a first conductivity type, a base of a second conductivity type and an emitter of a first conductivity type. Collector-emitter current paths of the bipolar transistors are connected in series to each other between first and second potentials, with a connection node providing an output of the composite circuit. Field effect transistors are respectively coupled between the bases and collectors of the bipolar transistors for controlling the on-off states of the bipolar transistors in opposite relationship to one another in response to an input signal provided to the composite circuit. Also, discharge arrangements are provided for the bases of the first and second bipolar transistors to discharge parasitic capacitance in the bases of the first and second bipolar transistors when they are turned off.

Self-aligned isolation double-gate FET

Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.

Variable delay circuit for emulating word line delay

Abstract: A semiconductor memory having an address buffer (10), row decoder (12), word lines (16), bit line (20) and sense amplifier (22) for accessing individual memory cells in an array of memory cells. In order to emulate worst case delays experienced in the word lines in accessing the last cells in the rows in order to prevent the sense amplifiers (22) from reading the bit lines (20) too soon, a tunable delay circuit (30) delays actuation of the sense amplifier. This circuit is divided into a plurality of impedance section with associated parasitic capacitance where groups of sections are bypassed by switching devices such as MOS transistors. The delay of a signal propagating through this tunable delay circuit can be varied by bypassing varying numbers of the sections with the switching devices.