Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Use of gas as low-k interlayer dielectric in LSI's: Demonstration of feasibility

Abstract: Reduction of the wire capacitance in LSI's has become an issue of the utmost importance since the wire parasitic capacitance plays a significant role in determining both chip speed and power. Low dielectric constant materials such as SiOF (k=3.3) are already in use in manufacturing, while other materials with lower dielectric constants (k=2.0/spl sim/3.0) are under development. Technology for further reduction of the dielectric constant, however, has not been reported so far. In this paper, we propose a gas-dielectric process that has the potential to achieve almost the minimum physically possible value for the dielectric constant: 1.0. The conceptual feasibility of the process is demonstrated, and basic process characterization data are presented. In addition, issues to be considered when integrating the proposed process into LSI manufacturing are identified, and work currently in progress addressing these issues is discussed.

Method of manufacturing a thin film transistor with reduced parasitic capacitance and reduced feed-through voltage

Abstract: A method of producing an improved thin film transistor structure is provided having no source/gate or drain/gate overlap. A laser-assisted doping technique is applied to fabricate such transistors. A radiation filter is employed, which is transparent to light at the photolithography wavelength, but reflective or opaque at the laser wavelength. Eliminating source/gate and drain/gate overlap significantly reduces or eliminates parasitic capacitance and feed-through voltage between source and gate. Short-channel a-Si:H thin film transistors may be obtained having high field effect mobilities. Improved pixel performance and pixel-to-pixel uniformity is provided.

Liquid crystal display device capable of reducing image flicker and method for driving the same

Abstract: A method for driving a liquid crystal display adjusts the falling edges of the gate driving signals for reducing image flicker. A first gate driving signal falls from a high level to a first level at the signal falling edge. A second gate driving signal falls from the high level to a second level at the signal falling edge. When the parasitic capacitance of a first pixel is larger than that of a second pixel, the first level is lower than the second level; when the parasitic capacitance of the first pixel is substantially the same as that of the second pixel, the first level is the same as the second level; when the parasitic capacitance of the first pixel is smaller than that of the second pixel, the first level is higher than the second level.

Self-Aligned U-Gate Carbon Nanotube Field-Effect Transistor with Extremely Small Parasitic Capacitance and Drain-Induced Barrier Lowering

Abstract: A novel self-aligned U-gate structure for carbon nanotube (CNT) field-effect transistors (FETs) is introduced and shown to yield excellent dc properties and high reproducibility that are comparable with that of the best CNT FETs based on the previously developed self-aligned device structures. In particular the subthreshold swing of the U-gate FET is 75 mV/dec and the drain-induced barrier lowering is effectively zero, indicating that the electrostatic potential of the whole CNT channel is most efficiently controlled by the U-gate and that the CNT device is a well-behaved FET. Moreover the high-frequency response of the U-gate FET is investigated, and the parasitic capacitance of the device is measured and shown to be one magnitude smaller than that of the previously developed self-aligned device structures. Direct frequency domain measurements show that the U-gate CNT FETs can operate up to 800 MHz, which is also higher than previously reported values. The large improvement in the device high-frequency behavior is largely due to the replacement of the high-κ dielectric material between the source/drain and the gate by a vacant space with κ ≈ 1, and the significant reduction in the device parasitic capacitance renders the U-gate CNT FETs promising for rf applications.

EL display panel driving method

Abstract: In order to charge and discharge parasitic capacitance of a source signal line sufficiently and program a predetermined current value into a pixel transistor, it is necessary to output a relatively large current from the source driver circuit. However, if such a large current is passed through the source signal line, the value of this current is programmed into the pixel, causing a larger than desired current to flow through an EL element. For example, if a 10 times larger current is used for programming, a 10 times larger current flows through the EL element, and thus the EL element illuminates 10 times more brightly. To obtain predetermined emission brightness, the time during which the current flows through the EL element can be reduced to 1/10 of one frame (1 F). This way, the parasitic capacitance of the source signal line can be charged and discharged sufficiently and the predetermined emission brightness can be obtained.