Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

A ULSI 2-D capacitance simulator for complex structures based on actual processes

Abstract: A two-dimensional (2-D) capacitance simulator for ultra-large-scale integrated (ULSI) circuits using an improved boundary-element method (BEM) is described. The capacitance simulator was linked with a topography/process simulator to estimate the distributed capacitances of complex structures based on actual processes. The utilization of a linear discontinuous element as the shape function is proposed in order to deal with multiregional problems by BEM. Other techniques employed in the simulation program, which enable precise calculation within practical CPU time, are also described. The calculated capacitances show good agreement with the experimental results. >

Method for making CMOS device having reduced parasitic capacitance

Abstract: A CMOS device having reduced parasitic junction capacitance and a process for fabrication of the device. The device includes an a portion (20') of an undoped epitaxial layer (20) vertically separating source and drain regions (52 and 53, 54 and 55) from buried layers (16, 18) formed in a semiconductor substrate (12). The undoped epitaxial layer (20) reduces the junction capacitance of the source and drain regions by providing an intrinsic silicon region physically separating regions of high dopant concentration from the source and drain regions. Additionally, MOS transistors fabricated in accordance with the invention have fully self-aligned channel regions extending from the upper surface (22) of the undoped epitaxial layer (20) to the buried layers (16, 18) residing in the semiconductor substrate (12).

Bipolar tunable transconductance element

Abstract: The present invention is a new design for transconductance elements useful in high-frequency filters such as fully differential state-variable biquads. The present invention enjoys a large dynamic range. It is built with simple circuitry to reduce parasitic capacitance which impedes high-frequency operation. It is easily tunable for use in programmable filters. It is configured in a fully differential circuit and operates on five volts. The present invention is also very useful for implementing dual-input or multiple input transconductance elements. By incorporating additional current sources in the present invention, another degree of freedom is added to the determination of pole frequency and pole quality factors, when the transconductance is used as a biquad filter building block.

A self-balancing circuit to measure capacitance and loss conductance for industrial transducer applications

Abstract: This paper describes a capacitance and loss conductance measuring circuit for the use in industrial transducers. The circuit is based on self-balancing principle and it is immune to stray capacitance. The balancing process is controlled by a micro-controller. The capacitance and loss conductance are represented by the digital feedback signals or by the combination of the feedback signals with the forward path signals. Experimental results show that the circuit has high resolution (0:04 fF) and good linearity (0.999).

An Optimum Design for Integrated Switched-Capacitor Dickson Charge Pump Multipliers With Area Power Balance

Abstract: This letter expands upon an optimum design of integrated switched-capacitor Dickson charge pump multipliers for minimizing the power, which considers the parasitic capacitance of both the top and bottom plates of pump capacitors. This letter also discusses an optimum design with area power balance, and suggests that the number of stages should be e NMIN, where e is 1.5-1.7 and NMIN is the minimum number of stages required to meet the condition that the output current is zero at a given output voltage.