Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Crosstalk canceling pattern for high-speed communications and modular jack having the same

Abstract: Disclosed herein are a crosstalk canceling pattern for high-speed communications and a modular jack having the same, which includes a compensating capacitor on a transmission line to cancel crosstalk due to parasitic capacitance generated between neighboring insert pins, and includes a second compensating capacitor to correct phase mismatch due to parasitic inductance generated in insert pins and transmission lines, when a high-frequency signal is applied The modular jack having the crosstalk canceling pattern for high-speed communications includes a housing, a printed circuit board, a lower contact block, and an upper contact block The hosing includes a plug insert hole, an insert pin locking plate, and a coupling guide part The printed circuit board is a multi-layered structure having a plurality of compensating capacitors The lower contact block is mounted to the lower surface of the printed circuit board The upper contact block is mounted to the upper portion of the lower contact block, and divides UTP cable wires to be connected to IDC terminals

High frequency sputtering device

Abstract: The stray capacitance between the target and grounding member and the loss of high frequency electric current are reduced by arranging dielectric members and metal members with a particular configuration at the circumference of the cathode and target

CODYMOS frequency dividers achieve low power consumption and high frequency

Abstract: Frequency dividers made with complementary dynamic m.o.s. (CODYMOS) circuits require only a small number of transistors and interconnections, a single input signal and operate with a minimum number of successive transitions. This leads to a drastic reduction in stray capacitance and current consumption, and to an increase in speed. A simplified analysis of these quantities is given for binary and ternary dividers. An experimental circuit, integrated with silicon-gate technology, operates from a 1.35 V battery, divides by 3 up to an input frequency in excess of 20 MHz and draws a current of 0.4 µA/MHz.

Non-contact coupling plate for circuit board tester

Abstract: A circuit circuit tester is provided for testing circuit runs of a circuit board for electrical continuity and electrical shorts. An electrical probe connected to one side of a capacitance meter is used to contact a particular circuit run, and an electrically conductive plate connected to the other side of the capacitance meter is maintained co-planar with and in close proximity to the circuit board to provide a suitable ground in the electrical test circuit, the capacitance of which circuit is a function of the electrical integrity of the circuit run. The measured capacitance is compared to a predetermined capacitance value for an identical circuit run of known acceptable quality to determine the electrical integrity of the tested circuit run.

Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications

Abstract: This work discusses the capacitance–voltage (C–V) analysis and frequency dependent capacitance of In2O5Sn (Tin Oxide) gate electrode Recessed Channel (TGRC) MOSFET with an aim to examine the effectiveness of In2O5Sn (Transparent) as a gate material on parasitic capacitance which prominently influences the current driving capability and thus, the switching performance. Moreover, capacitance dependent parameters such as Transconductance Frequency Product (TFP), Energy Delay Product (EDP) and Gain Bandwidth Product (GBP) are also assessed and found that, TFP increases to 6.33 times in comparison to metal gate RC MOSFET owing to a noticeable reduction in parasitic capacitance (Cgg = Cgs + Cgd), due to which EDP and GBP also improve considerably and thus reflects its effectiveness in RF amplifiers and receivers. In addition, the effect of parameter variation such as gate length (Lg) and negative junction depth (NJD) of TGRC is also observed, and results reveal that with Lg = 20 nm and NJD = 5 nm, TGRC unveils outstanding switching performance which is desirable for low power ULSI applications.