Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Tuning an RFID reader with electronic switches

Abstract: A reader for an RFID system includes a signal driver for generating an excitation signal and a resonant circuit having an adjustable resonant circuit capacitance for retuning the resonant circuit in response to detuning. The resonant circuit has a capacitance tuning circuit which includes a fine-tuning capacitor having a fine-tuning capacitance and a fine-tuning capacitor switch having an open position and a closed position. The fine-tuning capacitance is added to the adjustable resonant circuit capacitance when the fine-tuning capacitor switch is in the closed position and is removed from the adjustable resonant circuit capacitance when the fine-tuning capacitor switch is in the open position.

Layout for stable high speed semiconductor memory device

Abstract: In a semiconductor memory device, a memory cell array is separated into at least two portions on a substrate, and a serial memory element, such as a shift register, and control signal lines are collectively disposed between the two memory cell array portions, and by this arrangement, the length of the control signal lines and data lines can be minimized so that the stray or parasitic capacitance is reduced, and a higher speed and stable operation of the device is thereby realized

Design of a sense circuit for low-voltage flash memories

Abstract: A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and successfully operated at a low voltage of 1.5 V.

Interfacing control circuit with active circuit charge or discharge

Abstract: An interface control circuit comprising a buffer, an inverter, an OR gate and delay means. The interface control circuit can be utilized in digital systems for communication handshaking such that a buffer output current will actively flow through line stray capacitance thereby greatly reducing the rise time from a LOW state to a HIGH state, or charges in the line stray capacitance will actively discharge through the buffer means if negative logic mode is used thereby enabling a great reduction in fall time, therefore a much faster and efficient digital system can be obtained through the use of the invention.

New negative resistance regime of heterostructure insulated gate transistor (HIGFET) operation

Abstract: We present experimental evidence for negative differential resistance in n-channel heterostructure insulated gate transistors (HIGFET's) at high gate voltages. The negative resistance is explained by an increase in the gate current related to the electron heating in the two-dimensional electron gas. This mechanism is similar to that causing the negative differential resistance in NERFET's. However, much smaller parasitic capacitance in HIGFET's may allow us to reach higher frequencies of operation.