Topic
Parasitic capacitance
About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.
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Papers
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TL;DR: In this paper, an adaptive shunt damping circuit for improved damping performance is proposed. But the authors do not consider a single degree-of-freedom oscillator, and their analysis is performed based on the typical assumptions of the single degree of freedom oscillator and the ratio between the negative capacitance and piezoelectric capacitance.
36 citations
27 Jun 1983
TL;DR: This paper describes a hierarchical MOS layout verification program called IV, which extracts a circuit netlist from a MOS Layout Verification program and then compares this netlist to a reference circuitNetlist obtained from a schematic.
Abstract: This paper describes a hierarchical MOS layout verification program called IV. IV extracts a circuit netlist from a MOS layout and then compares this netlist to a reference circuit netlist obtained from a schematic. The circuit extraction phase of IV is described in detail. A unique characteristic of the program is the treatment of parasitic capacitance. IV is currently being used in a production environment to extract circuits in a variety of NMOS and CMOS processes.
36 citations
TL;DR: A method to adjust the ac winding capacitance of high-voltage high-frequency transformers by means of winding-rectifier integration is described, showing that it is virtually free to choose between ac and dc capacitances during the design stage.
Abstract: In this paper, a method to adjust the ac winding capacitance of high-voltage high-frequency transformers by means of winding-rectifier integration is described. First, a theoretical background to the method is given. From the theory, an equivalent circuit describing the characteristics of the combination of the transformer and the rectifier is derived. The derived circuit introduces the concept of a dc capacitance. Finally, the equivalent circuit and the method itself are verified by means of experiments on a transformer-rectifier system from an industrial application with the ratings 70 kV, 30 kW, and 25 kHz. The results from the experiments show that it is possible to vary the ac component of the winding capacitance from a few percent up to 95% of the total winding capacitance. This means that it is virtually free to choose between ac and dc capacitances during the design stage. This is very important in applications such as resonant converters with transformers having secondary windings connected to rectifiers with capacitive output filters.
36 citations
05 Jun 2002
TL;DR: New all digital-transistor CMOS very high DC-gain amplifiers that use internal positive-feedback technique are presented, which don't require perfect matching of transistors to achieve thevery high DC gain, and have a very low gain sensitivity to output swing.
Abstract: New all digital-transistor CMOS very high DC-gain amplifiers that use internal positive-feedback technique are presented. These structures don't require perfect matching of transistors to achieve the very high DC gain, and have a very low gain sensitivity to output swing. An implementation of a sample and hold circuit constructed using one of the proposed amplifiers is described. Special layout pattern is used to cut the parasitic capacitance.
36 citations
Patent•
06 May 2002TL;DR: In this article, a dual-mode, substantially planar antenna with a dipole or monopole structure for receiving and transmitting high-frequency signals is presented. But the antenna is not suitable for combined 5.5 GHz and 2.4 GHz operations.
Abstract: A dual mode, substantially planar antenna utilizes a dipole or monopole structure for receiving and transmitting high-frequency signals. Layers of conductive strips are disposed on opposite sides of an insulating (dielectric) substrate, such as printed circuit board material. First and second antenna elements are connected via an LC trap, the first antenna element corresponding to a first mode and the combined elements corresponding to a second mode. The LC trap is a single component inductor with parasitic capacitance sufficient to implement the LC trap or a set of patterns printed on the substrate. In one embodiment, the LC trap is constructed with only a single via through the substrate. The antenna is ideally suited for combined 5.5 GHz and 2.4 GHz RF operations.
36 citations