Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Semiconductor device and method of fabricating the same

Abstract: The present invention is provided to a semiconductor device and a method of fabricating the same A spacer consisting of SiCxHy or SiOCxHy having a low dielectric constant is formed at the sidewall of a trench or a hole that is formed in an interlayer insulating film It is therefore possible to reduce the dielectric constant while reducing critical dimension loss of the trench or the hole Therefore, the present invention has advantages that it can enhance the operating speed of the device by minimizing parasitic capacitance and prohibiting RC delay and crosstalk

Electrical Capacitance Tomography With Differential Sensor

Abstract: In electrical capacitance tomography, capacitance changes are used to determine the permittivity distribution in the imaging area. However, the changes are small compared with the standing capacitances, e.g., usually in the order of 10%–30%. For a single channel capacitance sensor, a differential configuration having a redundant pair of electrodes can be used to cancel the standing capacitance. However, there has been no report so far introducing such differential configuration into electrical capacitance tomography (ECT) sensors. This is mainly due to the fact that an ECT sensor is composed of an array of electrodes, e.g., 8, 12, and 16 and the capacitance measurements in ECT are required to interrogate capacitances of all electrode pair combinations, which introduce significant difficulty for a differential configuration. In this paper, a novel differential ECT sensor is proposed and designed, which consists of concentrically arranged dual array electrodes. It can also be thought as an additional array of electrodes being inserted between the measuring electrodes and the outer screen of a conventional ECT sensor. The new sensor design has been validated by the numerical simulation. A prototype sensor has been developed and evaluated with an field programmable gate arrays (FPGA)-based ECT measurement system, showing that with the proposed differential sensor, the dynamic range of the measured capacitance is reduced by $\sim 80$ % and an average improvement of 10.8 dB in signal-to-noise ratio is achieved.

Methods and apparatus for extracting parasitic capacitance values from a physical design of an integrated circuit

Abstract: Computer-implemented methods and apparatus for extracting and computing parasitic capacitance values and capacitances respectively, from a physical design of an integrated circuit are described. In one embodiment, the physical design comprises a plurality of layered conductors which are disposed within a first dielectric material. At least one conductor of the plurality of conductors is identified, and for the identified conductor, the first dielectric material is replaced for calculational purposes with a second (fictitious) dielectric material having a dielectric constant which is higher than the dielectric constant of the replaced dielectric material. In general, the second dielectric may have a different dielectric constant for each identified layer or elevation. Parasitic capacitance values are then computed for the integrated circuit. In a preferred embodiment, spaced-apart conductors at a common substrate elevation are identified, and a distance between the conductors is determined. If the determined distance exceeds a predetermined distance value, the first dielectric material is replaced with the second dielectric material. Such provides a basis for extracting parasitic capacitance values and computing one or more parasitic capacitances which more accurately represents the effect of the presence of fill structures within the physical integrated circuit.

The Cross-Coupled Pair?Part III [A Circuit for All Seasons]

Abstract: In this article, we study applications of the cross-coupled pair (XCP) in analog and RF circuits The XCP can serve as a negative resistance or a negative impedance converter in small-signal operation, or a regenerative circuit in large-signal operation

Parameterized analysis of Zero Voltage Switching in resonant converters for optimal electrode layout of Piezoelectric Transformers

Abstract: Ring shaped PTs (piezoelectric transformers) are an attractive alternative to magnetics in power converters. The achievable energy efficiency is 98% and the power density is up to 30 W/cm3. Additionally power supplies based on PTs display low levels of conducted and radiated EMI due to power conversion based on the piezoelectric effect. Rooted in the physics of this effect, both the in- and output terminal of a PT has a noticeable parasitic capacitance. In a common half-bridge power stage without any supporting magnetic components, the input parasitic capacitance can lead to hard switching losses that are in the range of the actual power rating of a specific PT. In this paper it is demonstrated how the electrode layout of a PT can be designed to enable ZVS (zero voltage switching). This optimization is made simple with a novel set of accurate and simple symbolic equations which relates ZVS constraints to the physical electrode layout of a PT. These properties takes basis in the formulation of an equivalent electrical PT circuit that is valid around the frequency of operation.