Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

New Equivalent Circuit of the IPM-Type BLDC Motor for Calculation of Shaft Voltage by Considering Electric and Magnetic Fields

Abstract: Fast switching and common-mode voltage of the space vector pulse-width modulation inverter output create several parasitic capacitances according to the geometry of the motor. The windings emit the electric and magnetic flux inside of the motor. They create capacitance links and electromotive force (EMF) in the shaft, respectively. Those capacitance links and EMF generate a current through two bearings of the shaft and directly reduces the bearing lifetime. In this study, we propose a new design of equivalent circuit, taking into account all parasitic capacitor components.

Superconductor signal amplifier

Abstract: A superconductor signal amplifier which receives an extremely small high-frequency signal having a frequency of tens of GHz generated in a superconductive circuit, amplifies the voltage of the high-frequency signal without a decrease in frequency, and outputs the thus amplified high-frequency signal from the superconductive circuit. At an output part of a single flux quantum circuit using a flux quantum as a binary information carrier, there are provided a superconductive junction line for flux quantum transmission and a splitter for simultaneously producing two flux quanta from a flux quantum. According to the number of plural series-connected SQUIDs, a plurality of flux quantum signals are generated and input to the plural series-connected SQUIDs so that the SQUIDs are simultaneously switched to a voltage state. In each SQUID pair comprising two SQUIDs, a part of an inductor is shared by the two SQUIDs for reduction in inductance, thereby increasing an output voltage of the series-connected SQUIDs. Furthermore, a magnetic shielding film formed under each SQUID is electrically isolated from ground to prevent a signal delay due to a parasitic capacitance.

Timing circuit cad

Abstract: A method of generating a design for timing circuitry having plural rotary travelling wave component circuit sections, comprises the steps of first dividing an area to be serviced into regions each small enough for there to be negligible inter-region transmission-line delay at target operating frequency. The dividing perimeters of each said region are then divided into segments suitable for approximating lumped transmission-line LKR and relevant parameters determined so that time delays over each such segment are substantially equal to cycle time of desired frequency divided by twice the number of segments. The capacitance of each segment is determined to be substantially equal to the largest envisaged load capacitance (including or preferably differential load capacitance) plus loop-to-loop interconnect capacitance plus active device (say and usually transistor) capacitance of voltage-transition regenerative means and addition to unloaded segments of padding capacitance calculated substantially to match the lumped line capacitance, and pitch/width of differencial transmission-line conductors is calculated using Wheeler's formula constrained by metallization factor involved. Finally a suitable odd number of cross-overs of transmission-line conductors is ascertained to meet cross-talk desiderata and number of transmission line loops specified to cover the area to be serviced and their interconnections, say conveniently at corners of rectangular said regions; and account taken of up to all of interconnect inductance, conduction skin effects, cross-talk, and MOSFET parasitics at least for high frequency applications.

MOS Analog switch driven by complementary, minimally skewed clock signals

Abstract: An MOS analog switch utilizing two transmission gates which are compensated by a third transmission gate is provided. The transmission gates may be either single or complementary conductivity type transmission gates and are controlled by complementary clock signals. A method and apparatus for minimizing clock skew thereby reducing error voltages caused by parasitic capacitance are provided.

A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators

Abstract: A fast-wakeup bang-bang LC digital phase-locked loop (DPLL) suitable for low-power wireline applications is presented. The PLL uses a novel oscillator design to generate eight output phases using magnetic coupling. The fast-wakeup feature improves power efficiency by allowing PLL power-cycling while accommodating latency requirements. Fast lock upon wakeup is achieved by calibrating the phase of the feedback clock with respect to the reference clock using a first-order loop and is further assisted by on-the-fly adjustment of loop parameters. The eight-phase output clock is generated using a loop of four digitally-controlled oscillators (DCOs) that are magnetically coupled through a passive structure. This structure enables magnetic coupling among oscillators with 2x area improvement over the prior art. As a result, in addition to eliminating the noise and parasitic capacitance of active coupling devices, the compact design reduces parasitic wiring capacitance, which is a significant limitation in high-frequency coupled oscillator design. Implemented in a 40 nm CMOS technology, the design achieves a 40-reference-cycle (100 ns) lock time and a 16% tuning range while producing an 8-phase output clock with less than 2° quadrature phase error up to 25 GHz. Measured PLL jitter is 392 fs (integrated from 100 kHz to 100 MHz) at 25 GHz while drawing 64 mW of power, 23 mW of which is consumed in the multiphase DCO. The DPLL occupies a total area of 0.1 mm 2 .