Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Improved Transformerless Grid-Tied PV Inverter Effectively Operating at Twice the Switching Frequency With Constant CMV and Reactive Power Capability

Abstract: In this article, an improved single-phase transformerless inverter is presented, which obviates the leakage current issue to a great extent. The proposed solution uses the dc-bypass (H6 type) topology with a diode clamp circuit, operated by a modified unipolar pulse-width modulation (PWM) scheme. An advantage of reduced switching losses comes with the use of the modified unipolar PWM, which produces effective double switching frequency at the inverter output. Due to the PWM strategy and diode clamp circuit, the common-mode voltage (CMV) of the inverter is constant throughout the operation. Consequently, the ground leakage current is negligible even in the presence of high parasitic capacitance of photovoltaic (PV) panels. Further, the other desirable features of the grid-tied inverters, such as reactive power injection for grid stability and low-voltage ride through (LVRT) are not compromised with the proposed scheme. A combination of high efficiency, constant CMV (and hence, negligible leakage current) and reactive power feeding capability with low component count stand the proposed system out among the existing transformerless grid-tied systems. The design and working principle of the proposed system are discussed and analyzed in detail. Simulation and experiment results are included to validate the proposed solution and its merits.

Performance analysis of a 127-micron pixel large-area TFT/photodiode array with boosted fill factor

Abstract: Sensor fill factor is one of the key pixel design requirements for high performance imaging arrays. In our conventional imaging pixel architecture with a TFT and a photodiode deposited in the same plane, the maximum area that the photodiode can occupy is limited by the size of the TFT and the surrounding metal lines. A full fill factor array design was previously proposed using a continuous sensor layer1. Despite the benefits of 100% fill factor, when applied to large-area applications, this array design suffers from high parasitic line capacitances and, thus, high line noise. We have designed and fabricated an alternative pixel structure in which the photodiode is deposited and patterned over the TFT, but does not overlap with the lines underneath. Separating the diode from the TFT plane allows extra space for an additional TFT which can be used for pixel reset and clipping excessive charge in the photodiode developed under high illumination. This reduces memory effect by 250%. The yield and the reliability are expected to improve as well since the TFTs and lines are buried underneath the diode. With the increased fill factor, we collect 56% more electrons per pixel, thereby improving the signal to noise ratio. The maximum signal to noise ratio is achieved when the increased signal and the undesirable parasitic capacitance on the data line are best optimized. Linearity, sensitivity, leakage, and MTF characteristics of a prototype X-ray imager based on this architecture are presented.

CMOS image sensor with a low-power architecture

Abstract: A system of reducing power consumption in and active pixels sensor. The sensor is broken into different blocks, and each of the blocks is individually optimized. The optimization may include minimizing the parasitic capacitance on the readout bus, turning off biases when not in use, and operating in a way that minimizes static power consumption of different elements such as A/D converters.

Electric field proximity detector for floating and grounded targets

Abstract: An electric field proximity detector capable of detecting partially conductive or conductive objects regardless of their impedance to circuit ground. The detector has a sensor with a transmitting electrode, a receiving electrode, and at least one circuit ground electrode preferably arranged in a bulls-eye configuration with the ground electrode between the transmitter and receiver electrodes. With appropriate sizing, upon the approach of an object, a signal received by the receiving electrode decreases, at least until the object is within a threshold distance of the sensor. The size and positioning of the ground electrode further reduces the effects of stray capacitance.

Digital to analog converter with high output compliance

Abstract: The disclosure relates to a digital to analog converter capable of suppressing "glitches" or transient spikes in the analog output signal. The digital to analog converter includes a plurality of current switches corresponding to the number of digital input bit signals and a resistive ladder of the conventional R-2R configuration. The R-2R ladder network has a plurality of input ports each connected to the output of a corresponding current switch. Logic inputs to the current switches determine which of the current switches are to be turned on to supply reference currents to corresponding input ports of the ladder network which in turn decrements the received reference currents by a factor of 2 as they pass through each stage to provide an analog output signal at the output terminal of the converter. To improve the accuracy of D/A conversion of the invention, compensating capacitors affording delay time equalization are provided for the least and most significant bit positions as well as between each two adjacent bit positions. These compensating capacitors operate to compensate for the stray capacitance of each current switch due to the parasitic collector-base capacitance of switching transistors to thereby equalize the impedance of the ladder network as viewed from each input port of the ladder network to the output terminal of the converter.