Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Comparative analysis of nanoscale MOS device architectures for RF applications

Abstract: The suitability of nanoscale non-planar FinFETs and classical planar single and double gate SOI MOSFETs for rf applications is examined via extensive 3D device simulations and detailed interpretation. It is shown that although nanoscale FinFETs achieve higher values of intrinsic dc gain (nearly 20 dB higher than planar SG devices), they also present higher gate capacitance that severely undermines their rf performance. We also show that at large values of drain currents, well-designed conventional planar single and double gate SOI MOSFETs attain higher values of cut-off frequency compared to FinFETs, whereas at lower drain currents, a well-aligned planar double gate SOI MOSFET is the optimal structure. The reason for higher parasitic capacitance in FinFETs as compared to planar MOSFETs is examined in detail. An assessment of the impact of back gate misalignment on the rf performance of a 25 nm gate length planar double gate MOSFET indicates that a misalignment of 12 nm towards the source end is acceptable to give superior performance to a FinFET. The importance of source/drain extension region engineering in nanoscale FinFETs for ultra-low voltage analogue applications is also investigated. RF figures of merit for planar and vertical MOS devices are also compared based on layout-area calculations. The paper provides valuable design insights for optimizing device parameters for nanoscale planar and vertical MOSFETs.

Half-Bridge Voltage Swing Inverter With Active Power Decoupling for Single-Phase PV Systems Supporting Wide Power Factor Range

Abstract: Photovoltaic (PV) inverters form the backbone of PV generation. This paper proposes an all-film-capacitor, transformerless single-phase inverter for PV application. The topology is a combination of a front-end boost stage, a half-bridge (HB) inverter stage, and a buck–boost power decoupling stage. The grid ripple power is decoupled by a large swing of the HB capacitors along with a limited ripple on the dc link, thus reducing the capacitance requirement and converter volume. Being an HB-derived inverter, the high-frequency common mode leakage current through the PV parasitic capacitance is mitigated. Furthermore, the dc-link average is optimally controlled to ensure a higher efficiency over wide operating load and power factor range. To validate its operation, a Silicon Carbide based 1-kVA laboratory prototype is built and closed-loop experimental results are provided at 100/75 kHz switching frequency over wide operating conditions.

Crosstalk test unit and method of calibration

Abstract: A test unit for measuring crosstalk in twisted pair cable. The test unit has an output signal balance (OSB) circuit that compensates for parasitic capacitance at its output terminals. The OSB circuit has a voltage controlled capacitance connected in circuit with each output terminal to control the effective capacitance between the output terminals and ground. The bias voltage for the variable capacitances is calibrated by a method in which the voltage for one of the variable capacitors is held constant while the voltage for the other capacitor is varied in voltage levels. A test signal frequency sweep is applied to the test unit output terminals. First and second voltage values are obtained and a final bias voltage value is calculated from using these two values.

Semiconductor device and method of manufacturing the same

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure such that a polyimide resin is arranged below a pad electrode to reduce a parasitic capacitance, thereby solving the following problem that an electrode step disappears in a step difference of a polyimide surface, and it becomes hard to reduce the parasitic capacitance through the increase of the step difference.SOLUTION: In a semiconductor optical device, a compound semiconductor layer is laminated which includes an etching stop layer 32 and an active layer 36 and is laminated on a semiconductor substrate 2. A ridge 20 and a lower part 42 on both sides of the ridge are formed by etching to the active layer 36. A part positioned under the pad electrode 14 among the lower parts 42 is etched to the etching stop layer 32, thereby forming a recess 46. The polyimide resin layer 22 has, below the pad electrode 14, a thickness formed by the depth of the lower part 42, the height of a terrace part 48 and the depth of the recess 46. The parasitic capacitance is reduced by increasing the depth of the recess 46.

RF Characterization of Schottky Diodes in 65-nm CMOS

Abstract: Schottky diodes in 65-nm CMOS have been designed, measured up to 67 GHz, and modeled in the reverse-bias voltage range. An array of 8 × 8 minimum-sized parallel diode junctions is compared with a single-junction diode and to linear arrays of 3, 12, and 64 elements of the same total area. An iterative analysis method and a more detailed equivalent circuit than that used in previous work are developed to extract the junction capacitance, the stray capacitance, and the series resistances separately. Based on the equivalent circuit model, the extrapolation of the diode RF behavior to frequencies beyond the measurement range is discussed. The relevance of the cutoff frequency of the Schottky junction itself for evaluation of the suitability of the diodes in millimeter-wave and terahertz applications is explained.