Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

LCD and driving method thereof

Abstract: There are provided an LCD and a driving method thereof for charging each data line of the LCD with sufficient data voltage. The present invention has a switching device installed between every adjacent data line, and the switching device connects the data line before a gate-on voltage is applied to the gate line thereby pre-charging the data line by charge sharing effect between the connected adjacent data lines and significantly reducing the change of the data line voltage by parasitic capacitance.

Design and Characterization of ESD Protection Devices for High-Speed I/O in Advanced SOI Technology

Abstract: This paper focuses on the characterization, modeling, and design of electrostatic discharge (ESD) protection devices such as the gated diode, the bulk substrate diode, and the double-well field-effect diode (DWFED) in 45 nm silicon-on-insulator technology. ESD protection capabilities are investigated using very fast transmission line pulsing tests to predict a device's performance in charged device model (CDM) ESD events. Device capacitance, which is critical for high-speed input/output performance, is evaluated, and biasing schemes and processing techniques are proposed to reduce the parasitic capacitance during normal operating conditions. Technology computer-aided design simulations are used to interpret the physical effects. The implementation of devices for meeting CDM protection requirements is discussed. Evaluation results identify DWFED as a promising candidate for the pad-based local-clamping scheme.

Output circuit for a semiconductor amplifier element

Abstract: An output circuit for a semiconductor amplifier element having an output capacitance (20, )that is to be cancelled by a first LC circuit having a first inductance(22,) and a first capacitance (24,) said output circuit comprising an additional inductance circuit with an additional inductance (30) and an additional capacitance (32), said first inductance circuit and said additional inductance circuit compensating for the output capacitance (20) of the semiconductor amplifier element, while the first inductance (22) and the first capacitance (24)cancel out the second harmonics within the output signal of the semiconductor amplifier element.

Power supply having a chopper with an improved power factor

Abstract: A power supply with a full-wave rectifier and a chopper having an inductor and a transistor connected in series across the rectifier. The transistor is switched on and off providing an interrupted voltage which is applied across a smoothing capacitor, via a blocking diode, to produce a smoothed DC voltage for driving a load. When the transistor is turned on, current from the rectifier is drawn through the inductor. When the transistor is turned off, the current through the inductor is conducted, in a positive direction, to the smoothing capacitor. The inductor and parasitic capacitance inherently present in the chopper create oscillations which allow current to flow through the inductor in a negative direction. A controller turns the transistor on at a time when the current flows in the negative direction and turns the transistor off after a predetermined on-period so as to release the current through the inductor, thereby causing the current to first flow in the negative direction and then in the positive direction through the inductor during the on-period. An input current wave shaping circuit is provided so that for each on-period, the amount of current flowing continuously through the inductor in the negative direction occurring immediately after the turning on of the transistor is less than the amount of current flowing through the inductor in the positive direction.

DC/DC switching converter circuit

Abstract: A two switch, DC/DC converter provides sufficient inductive energy storage at the termination of the "on" period of each switch to alter the charge on the intrinsic and stray capacitance of the combination of switches producing zero voltage across the alternate switch prior to its turn on. A short dead-band between the turn on pulses provided by the control circuit allows time for this transition. Thus the energy stored in the capacitance of the switches is returned to the source and load rather than being dissipated in the switching devices. This greatly improves the efficiency of the converter particularly when operating at high frequency. The unique topology of the converter provides other new and useful characteristics in addition to zero voltage switching capability such as operation at constant frequency with pulse-width-modulation for regulation, quasi-square wave output current, and the ability to integrate the magnetic elements with or without coupling.