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Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the double-layer printed spiral coil is used, which could fully take advantage of the limited space and make larger parasitic capacitance for lower resonant frequency, and the circuit model with consideration of parasitic parameters and high-frequency losses is built.
Abstract: As a critical part of the wireless power transfer system via strongly coupled magnetic resonances, the resonant coils must be cautiously designed for the specific resonant frequency and high quality factor. There are some issues needed to be considered and studied in the coil design, such as the coil structure, parasitic parameter extraction, and optimizing. In this paper, the double-layer printed spiral coil is used, which could fully take advantage of the limited space and make larger parasitic capacitance for lower resonant frequency. Using the simplified partial element equivalent circuit method and finite element method, the circuit model with consideration of parasitic parameters and high-frequency losses is built, and the impedance characteristic of coil is simulated, which coincides well with the measurement result. In addition, several elements affecting the high-frequency loss, including the skin effect, proximity effect, and dielectric loss, are discussed for reaching higher quality factor, which is critical for the power transfer system.

133 citations

Journal ArticleDOI
TL;DR: In this article, a circuit-oriented analysis technique that allows the parasitic capacitances to be replaced with linear equivalents is proposed to accommodate the well-established design and analysis techniques commonly used for linear circuits.
Abstract: Nonlinear, voltage-dependent capacitances of power semiconductor devices are capable of having significant impact on the operation of switched-mode power converters. Particularly at high switching frequency, these nonlinearities play a significant role in determining switching times, losses, and converter dynamics during switching transitions. In order to accommodate the well-established design and analysis techniques commonly used for linear circuits, this paper examines the nonlinear voltage-dependence of switching device capacitances and proposes a circuit-oriented analysis technique that allows the parasitic capacitances to be replaced with linear equivalents. The multitude of developed equivalents are verified through full nonlinear simulation in both MATLAB/Simulink and SPICE, as well as through experimental results.

133 citations

Patent
05 Jun 1998
TL;DR: In this paper, a zero current detector capable of detecting both forward and reverse zero current points facilitates the compensation of parasitic capacitance and parasitic oscillations is presented, which is well suited to integration with an inexpensive digital controller such as a microprocessor.
Abstract: A method and apparatus for controlling a boost converter, which offers improved power factor correction by compensating for the distorting effects of parasitic capacitance and parasitic oscillations. By precise adjustments to the closing time of the boost switch, the effects of parasitic capacitance can be reduced or eliminated. A zero current detector capable of detecting both forward and reverse zero current points facilitates the compensation. The method and circuit of the present invention are well-suited to integration with an inexpensive digital controller such as a microprocessor, and a method of dithering to enhance the time resolution of clocked digital circuits is presented.

127 citations

Patent
18 Jul 1996
TL;DR: In this article, a novel charge transfer switch and associated clocking scheme is proposed to reduce the supply current required to operate the charge pump, which reduces the power consumed by a system or circuit which has internal signals or nodes which are in opposite phase to each other.
Abstract: An efficient charge pump circuit. Increased efficiency compared to previous pump circuits is achieved through use of a novel charge transfer switch and associated clocking scheme which reduces the supply current required to operate the charge pump. Instead of repeatedly charging and discharging a stray capacitance of each pump stage capacitor, some of the charge stored in the stray capacitor on the clock driver side is transferred to the next pump stage. This serves to pre-charge the stray capacitor of the next stage, reducing the supply current required to operate the charge pump. The apparatus and method described can also be used to reduce the power consumed by a system or circuit which has internal signals or nodes which are in opposite phase to each other. This is accomplished by reducing the power used to charge and discharge a stray capacitance associated with the signals or nodes.

127 citations

Proceedings ArticleDOI
09 Oct 2009
TL;DR: A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch and a comparator with digital timing control offset cancellation is proposed.
Abstract: A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

127 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202364
2022156
2021179
2020344
2019380
2018382