Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Analysis of non-ideal characteristics of an ac-based capacitance transducer for tomography

Abstract: An ac-based capacitance transducer has been designed for use in electrical capacitance tomography systems. It has a high signal-to-noise ratio and good stray-immunity, compared with a charge/discharge transducer designed for the same purpose. However, the non-ideal characteristics of amplifiers and CMOS switches limit the performance of the ac-based transducer. This paper analyses the effects of the frequency-dependent gain of the amplifiers and the finite `on' resistance of the CMOS switches. It is shown that the non-ideal characteristics restrict the frequency response of the transducer by introducing extra poles, which depend not only on the parameters of the devices but also on the stray capacitance. Mathematical expressions quantifying these effects are presented.

Active matrix OLED driving circuit using current feedback

Abstract: An active matrix organic light emitting diode AMOLED driving circuit using current feedback that ensures the uniformity of brightness in pixels of a flat panel display and shortens the time required to input accurate current to respective pixels in the driving circuit The prevent invention provides an AMOLED driving circuit using current feedback, comprising: a current digital-to-analog converter outputting a current corresponding to input digital data; a first differential amplifier connected to the current digital-to-analog converter and controlling the input data current and a driving current of a driving transistor of a pixel circuit to be identical to each other; a current mirror mirroring driving current of an organic light emitting diode of the pixel circuit to an input side of the first differential amplifier; and a second differential amplifier coupled to the current mirror and controlling charge and discharge speeds of parasitic capacitance of the pixel circuit

Process of making self-aligned amorphous-silicon thin film transistors

Abstract: A thin film transistor structure and fabrication method for active matrix liquid crystal display. The structure is a self-aligned coplanar/staggered one. The feature of this structure is the self-aligned source and drain electrode to minimize the stray capacitance between the gate and the drain and the source. The source and drain electrodes are obtained by exposing negative photoresist on top of the transistor by incident light from the back of the transparent substrate using the gate electrode as a mask.

HPSAC—A silicided amorphous-silicon contact and interconnect technology for VLSI

Abstract: A high-performance silicided amorphous-silicon contact and interconnect technology (HPSAC) for VLSI is presented. In this novel scheme, a patterned silicide layer is used to form self-aligned contacts to the source/drain regions, as well as to interconnect devices. The fabrication procedures and some key processing techniques are described, Experimental results on n-and p-channel MOSFET's fabricated with HPSAC technology are presented. The performance improvement due to reduction of parasitic capacitance and resistance is discussed.

Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells

Abstract: Vertical tunnel field-effect transistors (VTFETs) have been extensively explored to overcome the scaling limits and to improve on-current (ION) compared to standard lateral device structures for the future technologies. The benefits in terms of reduced footprint, high ION and feasibility of fabrication have been demonstrated in several works. Among various VTFETs, the asymmetric heterojunction vertical tunnel FETs (HVTFETs) have emerged as one of the promising alternatives to standard transistors for low-voltage applications. However, while such device-level benefits without parasitics have been widely investigated, logic-gate design with parasitics and layout implications are not clear. In this article, we investigate and compare the layouts and parasitic capacitances and resistances of HVTFETs with FinFETs. Due to the vertical device structure of HVTFETs, a smaller footprint is observed compared to FinFETs in cells with small fan-in. However, for high fan-in cells, HVTFETs exhibit area overheads due to infeasibility of contact sharing in parallel and series transistors. These area overheads also lead to approximately 48p higher parasitic capacitance and resistance compared to FinFETs when the number of parallel and series connections increases. Further, in order to analyze the impact of parasitics, we modeled the analytical parasitics in SPICE. The models for both HVTFETs and FinFETs with parasitics were used to simulate a 15-stage inverter-based ring oscillator (RO) in order to compare the delay and energy. Our simulation results clearly show that HVTFETs exhibit less delay at a VDD