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Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.


Papers
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Journal ArticleDOI
TL;DR: In this article, the electrostatic gate capacitance of 1-D field effect transistors (FETs) with multiple cylindrical conducting channels is calculated using analytical models.
Abstract: This paper presents accurate analytical models to calculate the electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. Gate capacitance Cgg is decomposed into three major components: 1) capacitance Cgc between the gate and the parallel cylindrical conducting channels (the number of channels ges 1) in dual-layer dielectric materials; 2) outer fringe capacitance Cof between the gate and the source/drain cylinder conductors; and 3) coupling capacitance Cgtg between the adjacent gates. A realistic planar-gate structure with high-k gate dielectric material is considered in this paper, including the screening effect of the parallel conductors and different dielectric materials on capacitance. An accuracy of 10% is achieved from the analytic models, compared with the values that were simulated by 3-D numerical field solvers. Using a simple analytical expression for the gate delay that includes the parasitic capacitance and screening of multiple parallel conducting channels, this paper also shows that both increasing the number of channels per gate and reducing the gate height are effective ways to improve device speed.

119 citations

Journal ArticleDOI
TL;DR: The signal‐to‐noise ratio of a contactless conductivity detector for capillary electrophoresis was examined for different cell arrangements and operating parameters and it was shown that the best signal-to-noise ratios were achieved for the highest excitation voltage of 200 Vpp.
Abstract: The signal-to-noise ratio of a contactless conductivity detector for capillary electrophoresis was examined for different cell arrangements and operating parameters. The best signal-to-noise ratios, and hence the best detection limits, are obtained for frequencies which give highest sensitivity. Comparative experiments for three different excitation voltages (20, 100, and 200 V p p ) showed that the best signal-to-noise ratios were achieved for the highest excitation voltage of 200 V p p . Low conductivity of the background electrolyte solution is mandatory to obtain lowest noise levels, and also the improvement on applying high excitation voltages was best for the electrolyte solution with lowest conductivity. The diameter of the electrodes was found to have only a negligible effect, so that a tight fitting of the electrodes to the external diameter of the capillary is not necessary. A cell without shielding between the two electrodes showed significant direct coupling (stray capacitance) and lower signal-to-noise ratios for all experimental conditions used. A serious distortion of the peak shapes was also observed for this cell arrangement.

119 citations

Patent
28 Feb 1989
TL;DR: In this article, an SRAM using TiN local interconnects was proposed to reduce the moat parasitic capacitance and avoid the use of metal jumpers, resulting in increased density.
Abstract: An SRAM using TiN local interconnects. This permits the moat parasitic capacitance to be reduced, and also avoids use of metal jumpers, resulting in increased density.

118 citations

Patent
24 Sep 1997
TL;DR: In this article, a touch sensor switch that responds to touching, or even to the proximity of an object, is disclosed, and includes a number of capacitance elements, or touch pads, that produce an effective capacitance dependent upon the physical proximity of the object.
Abstract: A touch sensor switch that responds to touching, or even to the proximity of an object, is disclosed. The switch includes a number of capacitance elements, or touch pads, that produce an effective capacitance dependent upon the physical proximity of the object. A microcontroller under control of a program stored in a read-only memory causes its I/O port to set a transient voltage on each capacitance element as a logic level. Each transient voltage is at variance with the capacitive element's preferred voltage level. The program then reads the I/O port, and hence the logic levels of the capacitance elements, as the capacitive elements revert to their preferred voltage levels, and calculates the proximity of the object, or touching, from relationships among recorded signals. The circuit may also be embodied in an application specific integrated circuit.

118 citations

Patent
14 Oct 1998
TL;DR: An integrated circuit includes at least one porous silicon oxycarbide (SiOC) insulator (140, 305), which provides low dielectric constant (eR < 2) for minimizing parasitic capacitance as mentioned in this paper.
Abstract: An integrated circuit includes at least one porous silicon oxycarbide (SiOC) insulator (140, 305), which provides low dielectric constant (e.g., eR < 2) for minimizing parasitic capacitance. The insulator provides IC isolation, such as between circuit elements (115), between interconnection lines (300, 315), between circuit elements (115) and interconnection lines (300, 315), or as a passivation layer (320) overlying both circuit elements and interconnection lines.

117 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202364
2022156
2021179
2020344
2019380
2018382