Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.

Method for verification of crosstalk noise in a CMOS design

Abstract: In deep submicron technologies, coupling capacitance significantly dominates the total parasitic capacitance. This causes crosstalk noise to be induced on quiescent signals which could lead to catastrophic failures. A methodology is provided that is a practical approach to full-chip crosstalk noise verification. A grouping based method is described for identification of potential victims and associated aggressors, using either timing information or functional information. Potential victim signal lines are selected and pruned based on total coupling capacitance to various signal groups.

Capacitive switch and panel

Abstract: A user, touch actuable switch panel of the capacitive type that includes one or more touch actuable capacitive switches, each switch including at least two capacitive plate elements formed on a dielectric panel. Conductive paths formed on the dielectric panel interconnect the capacitive plate elements to a source for applying signals to the capacitive plate elements forming said capacitive switches and sensing a resulting change in signal level when a selected switch is actuated by the user. Trim tabs formed on the dielectric panel are provided to balance the effect of stray capacitance between the conductive paths and the capacitive plate elements to maintain the level of change of signal at a determined value upon the actuation of each of said one or more capacitive switches.

Integrated tunable inductance network and method

Abstract: An integrated, tunable inductance network features a number of fixed inductors fabricated on a common substrate along with a switching network made up of a number of micro-electromechanical (MEM) switches. The switches selectably interconnect the inductors to form an inductance network having a particular inductance value, which can be set with a high degree of precision when the inductors are configured appropriately. The preferred MEM switches introduce a very small amount of resistance, and the inductance network can thus have a high Q. The MEM switches and inductors can be integrated using common processing steps, reducing parasitic capacitance problems associated with wire bonds and prior art switches, increasing reliability, and reducing the space, weight and power requirements of prior art designs. The precisely tunable high-Q inductance network has wide applicability, such as in a resonant circuit which provides a narrow bandwidth frequency response which peaks at a specific predetermined frequency, making possible a highly selective performance low noise amplifier (LNA), or in an oscillator circuit so that a precise frequency of oscillation can be generated and changed as needed.

Vertical transistor with air-gap spacer

Abstract: A vertical transistor has a first air-gap spacer between a gate and a bottom source/drain region, and a second air-gap spacer between the gate and the contact to the bottom source/drain region. A dielectric layer disposed between the gate and the contact to the top source/drain decreases parasitic capacitance and inhibits electrical shorting.

FinFET performance advantage at 22nm: An AC perspective

Abstract: At the 22 nm node, we estimate that superior electrostatics and reduced junction capacitance in FinFETs may provide a 13~23% reduction in delay relative to planar FETs. However, this benefit is offset by enhanced gate-to-source/drain capacitance (Cgs) in FinFETs. Here, we measure FinFET Cgs capacitance at 22 nm-like dimensions and determine that, with optimization, the FinFET capacitance penalty can be limited to <6%, resulting in an overall advantage of up to 17% over a planar technology.