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Parasitic capacitance

About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.


Papers
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Journal ArticleDOI
TL;DR: Capacitance variations observed in the measurements can be mainly associated with the capacitance probed by the tip apex and not with positional changes of stray capacitance contributions, according to a comparison between experimental data and theoretical models.
Abstract: Nanoscale capacitance imaging with attofarad resolution (∼1 aF) of a nano-structured oxide thin film, using ac current sensing atomic force microscopy, is reported. Capacitance images are shown to follow the topographic profile of the oxide closely, with nanometre vertical resolution. A comparison between experimental data and theoretical models shows that the capacitance variations observed in the measurements can be mainly associated with the capacitance probed by the tip apex and not with positional changes of stray capacitance contributions. Capacitance versus distance measurements further support this conclusion. The application of this technique to the characterization of samples with non-voltage-dependent capacitance, such as very thin dielectric films, self-assembled monolayers and biological membranes, can provide new insight into the dielectric properties at the nanoscale.

88 citations

Journal ArticleDOI
TL;DR: In this article, the potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte Carlo simulations.
Abstract: The potential impact of high permittivity gate dielectrics on device short channel and circuit performance is studied over a wide range of dielectric permittivities (K/sub gate/) using two-dimensional (2-D) device and Monte Carlo simulations. The gate-to-channel capacitance and parasitic fringe capacitances are extracted using a highly accurate three-dimensional (3-D) capacitance extractor. It is observed that there is a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance in addition to an increase in internal fringe capacitance, when the conventional silicon dioxide is replaced by a high-K gate dielectric. The lower parasitic outer fringe capacitance is beneficial for the circuit performance, while the increase in internal fringe capacitance and the decrease in the gate-to-channel capacitance will degrade the short channel performance contributing to higher DIBL, drain leakage, and lower noise margin. It is shown that using low-K gate sidewalls with high-K gate insulators can decrease the fringing-induced barrier lowering. Also, from the circuit point of view, for the 70-nm technology generation, the presence of an optimum K/sub gate/ for different target subthreshold leakage currents has been identified.

88 citations

Patent
14 Jul 2004
TL;DR: In this paper, a photoelectric conversion element, a reading field-effect transistor, and a reset means for resetting the gate are provided on an insulating support body to prevent an output voltage from lowering due to increase of a parasitic capacitance.
Abstract: To prevent an output voltage from lowering due to increase of a parasitic capacitance when arranging a plurality of photoelectric conversion elements, a photoelectric conversion element, a reading field-effect transistor having a gate for receiving signal charges generated in the photoelectric conversion element and a source and a drain for reading a signal corresponding to signal charges accumulated in the gate, selection switch means set between the reading field-effect transistor and a power supply, and reset means for resetting the gate are provided on an insulating support body.

88 citations

Patent
21 Jul 1992
TL;DR: In this article, an improved diaphragm sensor employs silicon-on-silicon technology and has monolithic integrated signal conditioning circuitry, which minimizes the effects of stray capacitance and may be configured to provide either analog or digital output to external terminals.
Abstract: An improved diaphragm sensor employs silicon-on-silicon technology and has monolithic integrated signal conditioning circuitry. The support circuitry minimizes the effects of stray capacitance and may be configured to provide either analog or digital output to external terminals. It has a wide band of linearity and is particularly useful for accurately measuring pressures less than 0.5 PSI. The sensor is constructed by joining a silicon top plate having a mechanical pressure stop, a reduced thickness silicon diaphragm and a back plate having CMOS circuitry thereon. These components are bonded together by eutectic soldering.

87 citations

Journal ArticleDOI
08 Jul 2005
TL;DR: In this paper, a dead-time compensation strategy for a permanent magnet synchronous motor drive taking zero-current clamp and parasitic capacitance effects into account was proposed to improve the performance of DTCV around the zero crossing point of phase current.
Abstract: A dead-time compensation strategy is presented for a permanent-magnet synchronous motor drive taking zero-current clamp and parasitic capacitance effects into account To improve the performance of dead-time compensation around the zero-crossing point of phase current, two strategies are proposed One is to correct failure in polarity reversal of the dead-time compensation voltage (DTCV) caused by the zero-current clamp phenomenon The other is to adjust the amplitude of DTCV to deal with variation in transition time due to the parasitic capacitance of switching devices Experimental results demonstrate that current ripple for the proposed dead-time compensation strategy decreases by half compared with that of the conventional method

87 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202364
2022156
2021179
2020344
2019380
2018382