Topic
Parasitic capacitance
About: Parasitic capacitance is a research topic. Over the lifetime, 10029 publications have been published within this topic receiving 110331 citations.
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TL;DR: In this paper, a 7-junction electron pump was used as an electron counter with an error per pumped electron of 15 parts in 109 and an average hold time of 600 s. The accuracy and hold time are sufficient to enable a new fundamental standard of capacitance.
Abstract: We have operated a 7‐junction electron pump as an electron counter with an error per pumped electron of 15 parts in 109 and an average hold time of 600 s. The accuracy and hold time are sufficient to enable a new fundamental standard of capacitance. We compare the measured accuracy of the pump as a function of pumping speed and temperature with theoretical predictions based on a model which includes stray capacitance.
326 citations
01 Dec 2011
TL;DR: In this paper, a design methodology of ferroelectric (FE) negative capacitance FETs based on the concept of capacitance matching is presented, which, besides achieving sub-60mV/dec subthreshold swing, can significantly boost the oncurrent in exchange for a nominal hysteresis.
Abstract: A design methodology of ferroelectric (FE) negative capacitance FETs (NCFETs) based on the concept of capacitance matching is presented. A new mode of NCFET operation, called the “antiferroelectric mode” is proposed, which, besides achieving sub-60mV/dec subthreshold swing, can significantly boost the on-current in exchange for a nominal hysteresis. Design considerations for different device parameters (FE thickness, EOT, source/drain overlap & gate length) are explored. It is suggested that relative improvement in device performance due to FE negative capacitance becomes more significant in very short channel length devices because of the increased drain-to-channel coupling.
319 citations
TL;DR: In this article, a new family of switching amplifiers, each member having some of the features of both class E and inverse F, is introduced, which have class-E features such as incorporation of the transistor parasitic capacitance into the circuit.
Abstract: A new family of switching amplifiers, each member having some of the features of both class E and inverse F, is introduced. These class-E/F amplifiers have class-E features such as incorporation of the transistor parasitic capacitance into the circuit, exact truly switching time-domain solutions, and allowance for zero-voltage-switching operation. Additionally, some number of harmonics may be tuned in the fashion of inverse class F in order to achieve more desirable voltage and current waveforms for improved performance. Operational waveforms for several implementations are presented, and efficiency estimates are compared to class-E.
302 citations
TL;DR: In this article, the authors proposed a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to-band tunneling, which has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs.
Abstract: As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and VTHmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented.
299 citations
TL;DR: An improved interleaving structure with optimal behaviors is proposed, which constructs the top layer paralleling with the bottom layer and then in series with the other turns of the primary, so that a lower magnetomotive force ratio m can be obtained, as well as minimized ac resistance, leakage inductance, and even stray capacitance.
Abstract: The trend toward high power density, high operating frequency, and low profile in power converters has exposed a number of limitations in the use of conventional wire-wound magnetic component structures. A planar magnetic is a low-profile transformer or inductor utilizing planar windings, instead of the traditional windings made of Cu wires. In this paper, the most important factors for planar transformer (PT) design including winding loss, core loss, leakage inductance, and stray capacitance have individually been investigated. The tradeoffs among these factors have to be analyzed in order to achieve optimal parameters. Combined with an application, four typical winding arrangements have been compared to illustrate their advantages and disadvantages. An improved interleaving structure with optimal behaviors is proposed, which constructs the top layer paralleling with the bottom layer and then in series with the other turns of the primary, so that a lower magnetomotive force ratio m can be obtained, as well as minimized ac resistance, leakage inductance, and even stray capacitance. A 1.2-kW full-bridge dc-dc converter prototype employing the improved PT structure has been constructed, over 96% efficiency is achieved, and a 2.7% improvement, compared with the noninterleaving structure, is obtained.
295 citations